rvv: use Zba SHxADD where applicable

I don't know any hardware that would support the Vector extension and
yet would not support the Bit-manip extension (Zba + Zbb + Zbs), so this
should be fine.

modules/isa/riscv/deinterlace.c

@@ -36,7 +36,9 @@ static void Probe(void *data)
         struct deinterlace_functions *const f = data;
 
         f->merges[0] = merge8_rvv;
-        f->merges[1] = merge16_rvv;
+
+        if (vlc_CPU_RV_B())
+            f->merges[1] = merge16_rvv;
     }
 }
 

modules/isa/riscv/mixer.c

@@ -95,7 +95,7 @@ static int Probe(vlc_object_t *obj)
 {
     audio_volume_t *volume = (audio_volume_t *)obj;
 
-    if (!vlc_CPU_RV_V())
+    if (!vlc_CPU_RV_V() || !vlc_CPU_RV_B())
         return VLC_ENOTSUP;
 
     switch (volume->format) {

modules/isa/riscv/rvv_amplify.S

@@ -20,7 +20,7 @@
 
 #include "macros.S"
 
-	.option	arch, +v
+	.option	arch, +b, +v
 
 func	rvv_amplify_f32
 	lpad	0
@@ -30,13 +30,12 @@ func	rvv_amplify_f32
 #endif
 1:
 	vsetvli	t0, a2, e32, m8, ta, ma
-	slli	t1, t0, 2
 	vle32.v	v16, (a1)
-	add	a1, a1, t1
+	sh2add	a1, t0, a1
 	vfmul.vf	v16, v16, fa0
 	sub	a2, a2, t0
 	vse32.v	v16, (a0)
-	add	a0, a0, t1
+	sh2add	a0, t0, a0
 	bnez	a2, 1b
 
 	ret
@@ -50,13 +49,12 @@ func	rvv_amplify_f64
 #endif
 1:
 	vsetvli	t0, a2, e64, m8, ta, ma
-	slli	t1, t0, 3
 	vle64.v	v16, (a1)
-	add	a1, a1, t1
+	sh3add	a1, t0, a1
 	vfmul.vf	v16, v16, fa0
 	sub	a2, a2, t0
 	vse64.v	v16, (a0)
-	add	a0, a0, t1
+	sh3add	a0, t0, a0
 	bnez	a2, 1b
 
 	ret
@@ -67,13 +65,12 @@ func	rvv_amplify_i16
 	srli	a2, a2, 1
 1:
 	vsetvli	t0, a2, e16, m8, ta, ma
-	slli	t1, t0, 1
 	vle16.v	v16, (a1)
-	add	a1, a1, t1
+	sh1add	a1, t0, a1
 	vmulhsu.vx	v16, v16, a3
 	sub	a2, a2, t0
 	vse16.v	v16, (a0)
-	add	a0, a0, t1
+	sh1add	a0, t0, a0
 	bnez	a2, 1b
 
 	ret
@@ -84,13 +81,12 @@ func	rvv_amplify_i32
 	srli	a2, a2, 2
 1:
 	vsetvli	t0, a2, e32, m8, ta, ma
-	slli	t1, t0, 2
 	vle32.v	v16, (a1)
-	add	a1, a1, t1
+	sh2add	a1, t0, a1
 	vmulhsu.vx	v16, v16, a3
 	sub	a2, a2, t0
 	vse32.v	v16, (a0)
-	add	a0, a0, t1
+	sh2add	a0, t0, a0
 	bnez	a2, 1b
 
 	ret

modules/isa/riscv/rvv_merge.S

@@ -20,9 +20,7 @@
 
 #include "macros.S"
 
-	.option arch, +v
-	.text
-	.align	2
+	.option arch, +b, +v
 
 func	merge8_rvv
 	lpad	0
@@ -48,15 +46,14 @@ func	merge16_rvv
 	srli	a3, a3, 1
 1:
 	vsetvli	t0, a3, e16, m8, ta, ma
-	slli	t1, t0, 1
 	vle16.v	v16, (a1)
-	add	a1, a1, t1
+	sh1add	a1, t0, a1
 	vle16.v	v24, (a2)
-	add	a2, a2, t1
+	sh1add	a2, t0, a2
 	vaaddu.vv	v16, v16, v24
 	sub	a3, a3, t0
 	vse16.v	v16, (a0)
-	add	a0, a0, t1
+	sh1add	a0, t0, a0
 	bnez	a3, 1b
 
 	ret