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102 lines
4.8 KiB
102 lines
4.8 KiB
// See LICENSE for license details.
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#ifndef _RISCV_FP_EMULATION_H
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#define _RISCV_FP_EMULATION_H
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#include "emulation.h"
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#define GET_PRECISION(insn) (((insn) >> 25) & 3)
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#define GET_RM(insn) (((insn) >> 12) & 7)
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#define PRECISION_S 0
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#define PRECISION_D 1
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register long tp asm("tp");
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#ifdef __riscv_flen
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# define GET_F32_REG(insn, pos, regs) ({ \
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register int32_t value asm("a0") = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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uintptr_t tmp; \
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asm ("1: auipc %0, %%pcrel_hi(get_f32_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp), "+&r"(value) :: "t0"); \
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value; })
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# define SET_F32_REG(insn, pos, regs, val) ({ \
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register uint32_t value asm("a0") = (val); \
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uintptr_t offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
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uintptr_t tmp; \
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asm volatile ("1: auipc %0, %%pcrel_hi(put_f32_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp) : "r"(value), "r"(offset) : "t0"); })
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# define init_fp_reg(i) SET_F32_REG((i) << 3, 3, 0, 0)
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# define GET_F64_REG(insn, pos, regs) ({ \
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uintptr_t offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8, tmp; \
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int64_t value; \
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if (sizeof(uintptr_t) == 4) { \
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register int64_t* a0 asm("a0") = &value; \
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asm ("1: auipc %0, %%pcrel_hi(get_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp), "=m"(value) : "r"(offset), "r"(a0) : "t0"); \
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} else { \
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register int64_t a0 asm("a0") = offset; \
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asm ("1: auipc %0, %%pcrel_hi(get_f64_reg); add %0, %0, %1; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp), "+&r"(a0) :: "t0"); \
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value = a0; \
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} \
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value; })
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# define SET_F64_REG(insn, pos, regs, val) ({ \
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uintptr_t offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8, tmp; \
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if (sizeof(uintptr_t) == 4) { \
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uint64_t __val = (val); \
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register uint64_t* a0 asm("a0") = &__val; \
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asm volatile ("1: auipc %0, %%pcrel_hi(put_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp) : "r"(a0), "r"(offset), "m"(__val) : "t0"); \
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} else { \
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register uintptr_t a0 asm("a0") = (uintptr_t)(val); \
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asm volatile ("1: auipc %0, %%pcrel_hi(put_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp) : "r"(a0), "r"(offset) : "t0"); \
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} })
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# define GET_FCSR() read_csr(fcsr)
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# define SET_FCSR(value) write_csr(fcsr, (value))
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# define GET_FRM() read_csr(frm)
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# define SET_FRM(value) write_csr(frm, (value))
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# define GET_FFLAGS() read_csr(fflags)
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# define SET_FFLAGS(value) write_csr(fflags, (value))
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# define SETUP_STATIC_ROUNDING(insn) ({ \
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tp = read_csr(frm); \
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if (likely(((insn) & MASK_FUNCT3) == MASK_FUNCT3)) ; \
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else if (GET_RM(insn) > 4) return truly_illegal_insn(regs, mcause, mepc, mstatus, insn); \
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else tp = GET_RM(insn); \
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asm volatile ("":"+r"(tp)); })
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# define softfloat_raiseFlags(which) set_csr(fflags, which)
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# define softfloat_roundingMode ((int)tp)
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# define SET_FS_DIRTY() ((void) 0)
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#else
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# define GET_F64_REG(insn, pos, regs) (*(int64_t*)((void*)((regs) + 32) + (SHIFT_RIGHT(insn, (pos)-3) & 0xf8)))
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# define SET_F64_REG(insn, pos, regs, val) (GET_F64_REG(insn, pos, regs) = (val))
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# define GET_F32_REG(insn, pos, regs) (*(int32_t*)&GET_F64_REG(insn, pos, regs))
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# define SET_F32_REG(insn, pos, regs, val) (GET_F32_REG(insn, pos, regs) = (val))
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# define GET_FCSR() ({ (int)tp & 0xFF; })
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# define SET_FCSR(value) ({ asm volatile("add tp, x0, %0" :: "rI"((value) & 0xFF)); SET_FS_DIRTY(); })
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# define GET_FRM() (GET_FCSR() >> 5)
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# define SET_FRM(value) SET_FCSR(GET_FFLAGS() | ((value) << 5))
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# define GET_FFLAGS() (GET_FCSR() & 0x1F)
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# define SET_FFLAGS(value) SET_FCSR((GET_FRM() << 5) | ((value) & 0x1F))
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# define SETUP_STATIC_ROUNDING(insn) ({ \
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tp &= 0xFF; \
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if (likely(((insn) & MASK_FUNCT3) == MASK_FUNCT3)) tp |= tp << 8; \
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else if (GET_RM(insn) > 4) return truly_illegal_insn(regs, mcause, mepc, mstatus, insn); \
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else tp |= GET_RM(insn) << 13; \
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asm volatile ("":"+r"(tp)); })
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# define softfloat_raiseFlags(which) ({ asm volatile ("or tp, tp, %0" :: "rI"(which)); })
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# define softfloat_roundingMode ({ (int)tp >> 13; })
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# define SET_FS_DIRTY() set_csr(mstatus, MSTATUS_FS)
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#endif
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#define GET_F32_RS1(insn, regs) (GET_F32_REG(insn, 15, regs))
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#define GET_F32_RS2(insn, regs) (GET_F32_REG(insn, 20, regs))
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#define GET_F32_RS3(insn, regs) (GET_F32_REG(insn, 27, regs))
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#define GET_F64_RS1(insn, regs) (GET_F64_REG(insn, 15, regs))
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#define GET_F64_RS2(insn, regs) (GET_F64_REG(insn, 20, regs))
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#define GET_F64_RS3(insn, regs) (GET_F64_REG(insn, 27, regs))
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#define SET_F32_RD(insn, regs, val) (SET_F32_REG(insn, 7, regs, val), SET_FS_DIRTY())
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#define SET_F64_RD(insn, regs, val) (SET_F64_REG(insn, 7, regs, val), SET_FS_DIRTY())
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#define GET_F32_RS2C(insn, regs) (GET_F32_REG(insn, 2, regs))
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#define GET_F32_RS2S(insn, regs) (GET_F32_REG(RVC_RS2S(insn), 0, regs))
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#define GET_F64_RS2C(insn, regs) (GET_F64_REG(insn, 2, regs))
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#define GET_F64_RS2S(insn, regs) (GET_F64_REG(RVC_RS2S(insn), 0, regs))
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#endif
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