riscv-pk

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	3ed18cfbc7	Revert "Revert "SBI emulation of reads and writes to perf counters and config (#98 )"" This reverts commit `7ae86fb97b`. This will continue to allow accesses to cycle/time via mcycle/mtime despite https://github.com/riscv-software-src/riscv-isa-sim/pull/1297. The hope is this will keep most people happy while doing the right thing with Spike.	3 years ago
Andrew Waterman	7ae86fb97b	Revert "SBI emulation of reads and writes to perf counters and config (#98 )" This reverts commit `fd2ddce557`. The SBI took a different approach (explicit SBI call) to support writing the counters, rather than using traps.	5 years ago
Saleem Abdulrasool	e06e62f4a4	machine: replace `mbadaddr` with `mtval` (#242 ) The LLVM IAS does not support the older name for the `mtval` CSR. This updates the name to the current spelling, which is required to build with the LLVM IAS. This remains compatible with binutils as well.	5 years ago
Andrew Waterman	31878c5e2f	Make illegal-instruction jump table entries relative to their base This supports bbl living above 4 GiB.	7 years ago
Andrew Waterman	16476bd821	Properly license all nontrivial files	8 years ago
Zong Li	9d0911092d	Fix typo of perf counter (#100 )	8 years ago
Alex Solomatnikov	fd2ddce557	SBI emulation of reads and writes to perf counters and config (#98 )	8 years ago
Andrew Waterman	5f736b9ab8	Always write sbadaddr on trap redirection	9 years ago
Andrew Waterman	6f407a8d54	Attempt to read instruction from mbadaddr	9 years ago
Andrew Waterman	410fb0384f	New counter-enable scheme https://github.com/riscv/riscv-isa-manual/issues/10	9 years ago
Andrew Waterman	15a111444d	Emulate RVFC instructions	9 years ago
Andrew Waterman	f6b2274af4	avoid non-standard predefined macros	9 years ago
Andrew Waterman	6c1d0604dc	Use __riscv_flen macro to detect FP support	10 years ago
sashimi-yzh	292fb6e737	machine, emulation.c: fix the condition of rdtime emulation (#37 ) The time counter is enabled with the bit field set in `counteren` CSR.	10 years ago
Andrew Waterman	08a6142a04	Update to new counter spec	10 years ago
Andrew Waterman	7389e46cd0	Move DRAM to high addresses	10 years ago
Andrew Waterman	66776bbc3e	Remove mtime/mtimecmp	10 years ago
Andrew Waterman	d527883483	Misc improvements	10 years ago
Andrew Waterman	ccf79891f0	Factor emulation routines into multiple files	10 years ago
Andrew Waterman	b94c7a4b07	Refactor pk, bbl, machine into separate libraries Yuck.	10 years ago
Andrew Waterman	f5a96732cb	Fix ifdef guard on FCSR instructions	10 years ago
Andrew Waterman	80447e5711	Disentangle PK and BBL a bit	10 years ago
Andrew Waterman	bbc9a65fed	Begin refactoring emulation code	10 years ago
Andrew Waterman	fba40b7a8c	Use new counter-enable CSRs	10 years ago
Andrew Waterman	39c89b7db5	WIP on priv spec v1.9	10 years ago
Andrew Waterman	3c0620321d	WIP on priv spec v1.9	10 years ago
Andrew Waterman	d00cb5a541	Rely on __riscv_muldiv and __riscv_hard_float macros	10 years ago
Andrew Waterman	b0d83d2a84	Fix MULW/DIVW/etc. emulation code	10 years ago
Andrew Waterman	ad7a60abea	WIP on priv spec v1.9	10 years ago
Andrew Waterman	01fd29cb6e	Make PK compile on RV32 Of course, it doesn't work, because there's no support for fromhost/tohost devices in RV32.	11 years ago
Andrew Waterman	91058db5a6	Fix FP store emulation bug	11 years ago
Andrew Waterman	40668501fa	Fix some bugs in FP emulation	11 years ago
Andrew Waterman	6517fe26a2	Update to new privileged spec	11 years ago

20 Commits (47a2e87ccd4e95f80f0754c6f3312ccb3b90d916)