0d603acb91
[pk] load pk at addr 0; user stack top = MEMSIZE
15 years ago
ba0cf05466
[pk] fixed timer interrupt bug, etc.
15 years ago
04c8f1c003
[pk] fixed rv32 (dumb memset bug)
15 years ago
69ddca76d2
[pk] add cache flush after program load
15 years ago
64d0c6765c
[xcc,pk,sim] added privileged cflush instruction
15 years ago
85d1963000
[xcc,sim] rvc loads and stores
15 years ago
27afdf1a00
[sim,pk] fixed minor pk bugs and trap codes
15 years ago
7e6145731f
[xcc,sim,opcodes] more rvc instructions and bug fixes
15 years ago
5e7e315dee
[pk] fix init_fp function prototype
15 years ago
033e1e62bd
[pk] add vector_disabled trap handler
15 years ago
e23cce64e2
[xcc, sim] added rvc insn c.li; misc fixes
15 years ago
53eb346e31
[sim,pk] reorganized status register
15 years ago
6e7fe98ea9
[xcc,pk,sim,opcodes] added first RVC instruction
15 years ago
666ae0c9e5
[pk,fesvr] pk now loads elfs itself
this allows it to detect 32b binaries
15 years ago
c6fef75003
[opcodes,pk,sim,xcc] fix utidx - add rd
15 years ago
5eb059390c
[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem instructions
15 years ago
3706ca66d3
[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)
15 years ago
3cfe170bfa
[opcodes,pk,sim,xcc] add vector mem instructions
15 years ago
ae7b2fd190
[opcodes,pk,sim,xcc] add stop,utidx instructions
15 years ago
6145b13822
[opcodes,pk,sim,xcc] add fence instructions for vector unit
15 years ago
8520deaafc
[opcodes] minor opcode changes
15 years ago
c1a89d8055
[sim,pk,xcc,opcodes] removed fminmag/fmaxmag
15 years ago
4baf0c99c5
[xcc,pk,opcodes,sim] updated encoding/insn names
15 years ago
d9e887bd18
[pk] 32bit kernel + FPU emulation now compiles
15 years ago
9b215d8bb8
[xcc,opcodes,pk,sim] krste's re-renaming spree
15 years ago
ee82a98e99
[xcc,sim,opcodes] removed mtflh/mffl/mffh
in rv32 these will be replaced with loads and stores.
15 years ago
5c9d48945e
[sim,pk] added interrupt-pending field to cause reg
15 years ago
af2d471a4e
[pk] fixed FP emulation bug
kernel would erroneously trap on FP disabled
15 years ago
83cdb2063f
[sim,xcc,opcodes] added back mtflh.d
15 years ago
b8449c463e
[opcodes,pk,sim,xcc] synci now bombs whole icache
15 years ago
4385a34442
[xcc,opcodes,pk,sim] cleanup to FP ISA
- Added 5th rounding mode
- Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...)
- merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode
- made MFFL.D and MFFH.D illegal in RV64
15 years ago
9c3ff9eccd
[sim,opcodes] add mulhsu instruction
15 years ago
da568c7f5e
[opcodes,pk,sim,xcc] great renumbering of 2011, part deux
15 years ago
5a0bc797e3
[sim, pk, xcc, opcodes] great instruction renaming of 2011
15 years ago
99e15cd707
[opcodes, sim, xcc] made *w insns illegal in RV32
now generic variants behave differently in RV32 and RV64.
15 years ago
dff73c1d18
[opcodes, pk, sim, xcc] removed nor, normalized macros to addi
15 years ago
0cf0242c3b
[pk] added --disable-fp-emulation option for code size
15 years ago
b83d64df01
[opcodes,pk,sim,xcc] flip fields to favor little endian
15 years ago
5490b1d627
[pk] send stdout/stderr to both fesvr and debug console
15 years ago
37ed1d3297
[pk] fixed memset bug
16 years ago
63729473a5
[opcodes, pk, sim, xcc] Tweaked FP encoding
16 years ago
3f0c7368c8
[opcodes] generate latex and verilog correctly
16 years ago
e45fd54d56
[pk] minor PK bugfix
16 years ago
783c0ec831
[pk] various PK cleanups/speedups
16 years ago
16a55362ca
[xcc, sim, pk, opcodes] new instruction encoding!
16 years ago
4daccfc1cf
[xcc, sim, pk] link register is now x1
16 years ago
664411d5e6
[opcodes, pk, sim, xcc] made jumps shorter and PC-relative
16 years ago
9fe7d4f656
[pk,sim,xcc] get rid of at register, introduce tp register
16 years ago
6ba19295c0
[sim,xcc,pk,opcodes] static rounding modes for FP insns
Now, you can either use the RM in the FSR or specify it in the insn.
(Except for FP->int; no dynamic for that.)
16 years ago
f415fce416
[pk] assume FSR exists even if FP is unsupported
16 years ago
Andrew Waterman
Yunsup Lee
Andrew Waterman