riscv
/
riscv-pk
mirror of https://github.com/riscv-software-src/riscv-pk.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

Synced up PK with supervisor changes/asm syntax 

You must upgrade to the latest compiler and ISA
simulator to build and run this version of the PK.
eos14-bringup
Andrew Waterman 15 years ago
parent
2f5776b244
commit
8717517e04
10 changed files with 229 additions and 274 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 196
      pk/entry.S
  2. 132
      pk/fp_asm.S
  3. 30
      pk/handlers.c
  4. 50
      pk/pcr.h
  5. 12
      pk/pk.c
  6. 1
      pk/pk.h
  7. 26
      pk/pk.ld
  8. 6
      pk/riscv-opc.h
  9. 48
      pk/riscv-pk.S
  10. 2
      pk/syscall.c

196
pk/entry.S
View File

@ -15,60 +15,60 @@
save_tf: # write the trap frame onto the stack
# save gprs
STORE $x3,3*REGBYTES($x2)
STORE $x4,4*REGBYTES($x2)
STORE $x5,5*REGBYTES($x2)
STORE $x6,6*REGBYTES($x2)
STORE $x7,7*REGBYTES($x2)
STORE $x8,8*REGBYTES($x2)
STORE $x9,9*REGBYTES($x2)
STORE $x10,10*REGBYTES($x2)
STORE $x11,11*REGBYTES($x2)
STORE $x12,12*REGBYTES($x2)
STORE $x13,13*REGBYTES($x2)
STORE $x14,14*REGBYTES($x2)
STORE $x15,15*REGBYTES($x2)
STORE $x16,16*REGBYTES($x2)
STORE $x17,17*REGBYTES($x2)
STORE $x18,18*REGBYTES($x2)
STORE $x19,19*REGBYTES($x2)
STORE $x20,20*REGBYTES($x2)
STORE $x21,21*REGBYTES($x2)
STORE $x22,22*REGBYTES($x2)
STORE $x23,23*REGBYTES($x2)
STORE $x24,24*REGBYTES($x2)
STORE $x25,25*REGBYTES($x2)
STORE $x26,26*REGBYTES($x2)
STORE $x27,27*REGBYTES($x2)
STORE $x28,28*REGBYTES($x2)
STORE $x29,29*REGBYTES($x2)
STORE $x30,30*REGBYTES($x2)
STORE $x31,31*REGBYTES($x2)
STORE x3,3*REGBYTES(x2)
STORE x4,4*REGBYTES(x2)
STORE x5,5*REGBYTES(x2)
STORE x6,6*REGBYTES(x2)
STORE x7,7*REGBYTES(x2)
STORE x8,8*REGBYTES(x2)
STORE x9,9*REGBYTES(x2)
STORE x10,10*REGBYTES(x2)
STORE x11,11*REGBYTES(x2)
STORE x12,12*REGBYTES(x2)
STORE x13,13*REGBYTES(x2)
STORE x14,14*REGBYTES(x2)
STORE x15,15*REGBYTES(x2)
STORE x16,16*REGBYTES(x2)
STORE x17,17*REGBYTES(x2)
STORE x18,18*REGBYTES(x2)
STORE x19,19*REGBYTES(x2)
STORE x20,20*REGBYTES(x2)
STORE x21,21*REGBYTES(x2)
STORE x22,22*REGBYTES(x2)
STORE x23,23*REGBYTES(x2)
STORE x24,24*REGBYTES(x2)
STORE x25,25*REGBYTES(x2)
STORE x26,26*REGBYTES(x2)
STORE x27,27*REGBYTES(x2)
STORE x28,28*REGBYTES(x2)
STORE x29,29*REGBYTES(x2)
STORE x30,30*REGBYTES(x2)
STORE x31,31*REGBYTES(x2)
mfpcr $x3,ASM_CR(PCR_K0)
STORE $x3,1*REGBYTES($x2) # $x1 is in $PCR_K0
mfpcr $x3,ASM_CR(PCR_K1)
STORE $x3,2*REGBYTES($x2) # $x2 is in $PCR_K1
mfpcr x3,ASM_CR(PCR_K0)
STORE x3,1*REGBYTES(x2) # x1 is in PCR_K0
mfpcr x3,ASM_CR(PCR_K1)
STORE x3,2*REGBYTES(x2) # x2 is in PCR_K1
# get sr, epc, badvaddr, cause
mfpcr $x3,ASM_CR(PCR_SR) # sr
STORE $x3,32*REGBYTES($x2)
mfpcr $x4,ASM_CR(PCR_EPC) # epc
STORE $x4,33*REGBYTES($x2)
mfpcr $x3,ASM_CR(PCR_BADVADDR) # badvaddr
STORE $x3,34*REGBYTES($x2)
mfpcr $x3,ASM_CR(PCR_CAUSE) # cause
STORE $x3,35*REGBYTES($x2)
mfpcr x3,ASM_CR(PCR_SR) # sr
STORE x3,32*REGBYTES(x2)
mfpcr x4,ASM_CR(PCR_EPC) # epc
STORE x4,33*REGBYTES(x2)
mfpcr x3,ASM_CR(PCR_BADVADDR) # badvaddr
STORE x3,34*REGBYTES(x2)
mfpcr x3,ASM_CR(PCR_CAUSE) # cause
STORE x3,35*REGBYTES(x2)
# get faulting insn, if it wasn't a fetch-related trap
li $x5, CAUSE_MISALIGNED_FETCH
li $x6, CAUSE_FAULT_FETCH
beq $x3, $x5, 1f
beq $x3, $x6, 1f
lh $x3,0($x4)
lh $x4,2($x4)
sh $x3, 36*REGBYTES($x2)
sh $x4,2+36*REGBYTES($x2)
li x5, CAUSE_MISALIGNED_FETCH
li x6, CAUSE_FAULT_FETCH
beq x3, x5, 1f
beq x3, x6, 1f
lh x3,0(x4)
lh x4,2(x4)
sh x3, 36*REGBYTES(x2)
sh x4,2+36*REGBYTES(x2)
1:
ret
.end save_tf
@ -77,68 +77,68 @@ save_tf: # write the trap frame onto the stack
.ent pop_tf
pop_tf: # write the trap frame onto the stack
# restore gprs
LOAD $t0,32*REGBYTES($a0) # restore sr (should disable interrupts)
mtpcr $t0,ASM_CR(PCR_SR)
LOAD t0,32*REGBYTES(a0) # restore sr (should disable interrupts)
mtpcr t0,ASM_CR(PCR_SR)
LOAD $x1,1*REGBYTES($a0)
mtpcr $x1,ASM_CR(PCR_K0)
LOAD $x1,2*REGBYTES($a0)
mtpcr $x1,ASM_CR(PCR_K1)
move $x1,$a0
LOAD $x3,3*REGBYTES($x1)
LOAD $x4,4*REGBYTES($x1)
LOAD $x5,5*REGBYTES($x1)
LOAD $x6,6*REGBYTES($x1)
LOAD $x7,7*REGBYTES($x1)
LOAD $x8,8*REGBYTES($x1)
LOAD $x9,9*REGBYTES($x1)
LOAD $x10,10*REGBYTES($x1)
LOAD $x11,11*REGBYTES($x1)
LOAD $x12,12*REGBYTES($x1)
LOAD $x13,13*REGBYTES($x1)
LOAD $x14,14*REGBYTES($x1)
LOAD $x15,15*REGBYTES($x1)
LOAD $x16,16*REGBYTES($x1)
LOAD $x17,17*REGBYTES($x1)
LOAD $x18,18*REGBYTES($x1)
LOAD $x19,19*REGBYTES($x1)
LOAD $x20,20*REGBYTES($x1)
LOAD $x21,21*REGBYTES($x1)
LOAD $x22,22*REGBYTES($x1)
LOAD $x23,23*REGBYTES($x1)
LOAD $x24,24*REGBYTES($x1)
LOAD $x25,25*REGBYTES($x1)
LOAD $x26,26*REGBYTES($x1)
LOAD $x27,27*REGBYTES($x1)
LOAD $x28,28*REGBYTES($x1)
LOAD $x29,29*REGBYTES($x1)
LOAD $x30,30*REGBYTES($x1)
LOAD $x31,31*REGBYTES($x1)
LOAD x1,1*REGBYTES(a0)
mtpcr x1,ASM_CR(PCR_K0)
LOAD x1,2*REGBYTES(a0)
mtpcr x1,ASM_CR(PCR_K1)
move x1,a0
LOAD x3,3*REGBYTES(x1)
LOAD x4,4*REGBYTES(x1)
LOAD x5,5*REGBYTES(x1)
LOAD x6,6*REGBYTES(x1)
LOAD x7,7*REGBYTES(x1)
LOAD x8,8*REGBYTES(x1)
LOAD x9,9*REGBYTES(x1)
LOAD x10,10*REGBYTES(x1)
LOAD x11,11*REGBYTES(x1)
LOAD x12,12*REGBYTES(x1)
LOAD x13,13*REGBYTES(x1)
LOAD x14,14*REGBYTES(x1)
LOAD x15,15*REGBYTES(x1)
LOAD x16,16*REGBYTES(x1)
LOAD x17,17*REGBYTES(x1)
LOAD x18,18*REGBYTES(x1)
LOAD x19,19*REGBYTES(x1)
LOAD x20,20*REGBYTES(x1)
LOAD x21,21*REGBYTES(x1)
LOAD x22,22*REGBYTES(x1)
LOAD x23,23*REGBYTES(x1)
LOAD x24,24*REGBYTES(x1)
LOAD x25,25*REGBYTES(x1)
LOAD x26,26*REGBYTES(x1)
LOAD x27,27*REGBYTES(x1)
LOAD x28,28*REGBYTES(x1)
LOAD x29,29*REGBYTES(x1)
LOAD x30,30*REGBYTES(x1)
LOAD x31,31*REGBYTES(x1)
# gtfo!
LOAD $x2,33*REGBYTES($x1)
mtpcr $x2,ASM_CR(PCR_EPC)
mfpcr $x1,ASM_CR(PCR_K0)
mfpcr $x2,ASM_CR(PCR_K1)
LOAD x2,33*REGBYTES(x1)
mtpcr x2,ASM_CR(PCR_EPC)
mfpcr x1,ASM_CR(PCR_K0)
mfpcr x2,ASM_CR(PCR_K1)
eret
.end pop_tf
.global trap_entry
.ent trap_entry
trap_entry:
mtpcr $ra,ASM_CR(PCR_K0)
mtpcr $x2,ASM_CR(PCR_K1)
mtpcr ra,ASM_CR(PCR_K0)
mtpcr x2,ASM_CR(PCR_K1)
# when coming from kernel, continue below its stack
mfpcr $ra,ASM_CR(PCR_SR)
and $ra,$ra,SR_PS
add $x2, $sp, -320
bnez $ra, 1f
la $x2,stack_top-320
mfpcr ra,ASM_CR(PCR_SR)
and ra,ra,SR_PS
add x2, sp, -320
bnez ra, 1f
la x2,stack_top-320
1:jal save_tf
move $sp,$x2
move $a0,$x2
move sp,x2
move a0,x2
jal handle_trap
.end trap_entry

132
pk/fp_asm.S
View File

@ -5,40 +5,40 @@
.ent get_fp_state
get_fp_state:
mffsr $v0
mffsr v0
fsd $f0 , 0($a0)
fsd $f1 , 8($a0)
fsd $f2 , 16($a0)
fsd $f3 , 24($a0)
fsd $f4 , 32($a0)
fsd $f5 , 40($a0)
fsd $f6 , 48($a0)
fsd $f7 , 56($a0)
fsd $f8 , 64($a0)
fsd $f9 , 72($a0)
fsd $f10, 80($a0)
fsd $f11, 88($a0)
fsd $f12, 96($a0)
fsd $f13,104($a0)
fsd $f14,112($a0)
fsd $f15,120($a0)
fsd $f16,128($a0)
fsd $f17,136($a0)
fsd $f18,144($a0)
fsd $f19,152($a0)
fsd $f20,160($a0)
fsd $f21,168($a0)
fsd $f22,176($a0)
fsd $f23,184($a0)
fsd $f24,192($a0)
fsd $f25,200($a0)
fsd $f26,208($a0)
fsd $f27,216($a0)
fsd $f28,224($a0)
fsd $f29,232($a0)
fsd $f30,240($a0)
fsd $f31,248($a0)
fsd f0 , 0(a0)
fsd f1 , 8(a0)
fsd f2 , 16(a0)
fsd f3 , 24(a0)
fsd f4 , 32(a0)
fsd f5 , 40(a0)
fsd f6 , 48(a0)
fsd f7 , 56(a0)
fsd f8 , 64(a0)
fsd f9 , 72(a0)
fsd f10, 80(a0)
fsd f11, 88(a0)
fsd f12, 96(a0)
fsd f13,104(a0)
fsd f14,112(a0)
fsd f15,120(a0)
fsd f16,128(a0)
fsd f17,136(a0)
fsd f18,144(a0)
fsd f19,152(a0)
fsd f20,160(a0)
fsd f21,168(a0)
fsd f22,176(a0)
fsd f23,184(a0)
fsd f24,192(a0)
fsd f25,200(a0)
fsd f26,208(a0)
fsd f27,216(a0)
fsd f28,224(a0)
fsd f29,232(a0)
fsd f30,240(a0)
fsd f31,248(a0)
ret
@ -48,40 +48,40 @@ get_fp_state:
.ent put_fp_state
put_fp_state:
fld $f0 , 0($a0)
fld $f1 , 8($a0)
fld $f2 , 16($a0)
fld $f3 , 24($a0)
fld $f4 , 32($a0)
fld $f5 , 40($a0)
fld $f6 , 48($a0)
fld $f7 , 56($a0)
fld $f8 , 64($a0)
fld $f9 , 72($a0)
fld $f10, 80($a0)
fld $f11, 88($a0)
fld $f12, 96($a0)
fld $f13,104($a0)
fld $f14,112($a0)
fld $f15,120($a0)
fld $f16,128($a0)
fld $f17,136($a0)
fld $f18,144($a0)
fld $f19,152($a0)
fld $f20,160($a0)
fld $f21,168($a0)
fld $f22,176($a0)
fld $f23,184($a0)
fld $f24,192($a0)
fld $f25,200($a0)
fld $f26,208($a0)
fld $f27,216($a0)
fld $f28,224($a0)
fld $f29,232($a0)
fld $f30,240($a0)
fld $f31,248($a0)
fld f0 , 0(a0)
fld f1 , 8(a0)
fld f2 , 16(a0)
fld f3 , 24(a0)
fld f4 , 32(a0)
fld f5 , 40(a0)
fld f6 , 48(a0)
fld f7 , 56(a0)
fld f8 , 64(a0)
fld f9 , 72(a0)
fld f10, 80(a0)
fld f11, 88(a0)
fld f12, 96(a0)
fld f13,104(a0)
fld f14,112(a0)
fld f15,120(a0)
fld f16,128(a0)
fld f17,136(a0)
fld f18,144(a0)
fld f19,152(a0)
fld f20,160(a0)
fld f21,168(a0)
fld f22,176(a0)
fld f23,184(a0)
fld f24,192(a0)
fld f25,200(a0)
fld f26,208(a0)
fld f27,216(a0)
fld f28,224(a0)
fld f29,232(a0)
fld f30,240(a0)
fld f31,248(a0)
mtfsr $a1
mtfsr a1
ret

30
pk/handlers.c
View File

@ -99,30 +99,9 @@ void handle_fault_store(trapframe_t* tf)
panic("Faulting store!");
}
static void handle_bad_interrupt(trapframe_t* tf, int interrupt)
{
panic("Bad interrupt %d!",interrupt);
}
static void handle_timer_interrupt(trapframe_t* tf)
{
mtpcr(PCR_COMPARE, mfpcr(PCR_COMPARE)+TIMER_PERIOD);
}
static void handle_interrupt(trapframe_t* tf)
{
int interrupts = (tf->cause & CAUSE_IP) >> CAUSE_IP_SHIFT;
for(int i = 0; interrupts; interrupts >>= 1, i++)
{
if(interrupts & 1)
{
if(i == TIMER_IRQ)
handle_timer_interrupt(tf);
else
handle_bad_interrupt(tf,i);
}
}
panic("Timer interrupt!");
}
static void handle_syscall(trapframe_t* tf)
@ -148,7 +127,6 @@ void handle_trap(trapframe_t* tf)
[CAUSE_ILLEGAL_INSTRUCTION] = handle_illegal_instruction,
[CAUSE_PRIVILEGED_INSTRUCTION] = handle_privileged_instruction,
[CAUSE_FP_DISABLED] = handle_fp_disabled,
[CAUSE_INTERRUPT] = handle_interrupt,
[CAUSE_SYSCALL] = handle_syscall,
[CAUSE_BREAKPOINT] = handle_breakpoint,
[CAUSE_MISALIGNED_LOAD] = handle_misaligned_load,
@ -158,12 +136,12 @@ void handle_trap(trapframe_t* tf)
[CAUSE_VECTOR_DISABLED] = handle_vector_disabled,
[CAUSE_VECTOR_BANK] = handle_vector_bank,
[CAUSE_VECTOR_ILLEGAL_INSTRUCTION] = handle_vector_illegal_instruction,
[CAUSE_IRQ0 + TIMER_IRQ] = handle_timer_interrupt,
};
int exccode = (tf->cause & CAUSE_EXCCODE) >> CAUSE_EXCCODE_SHIFT;
kassert(exccode < ARRAY_SIZE(trap_handlers));
kassert(tf->cause < ARRAY_SIZE(trap_handlers) && trap_handlers[tf->cause]);
trap_handlers[exccode](tf);
trap_handlers[tf->cause](tf);
pop_tf(tf);
}

50
pk/pcr.h
View File

@ -1,8 +1,6 @@
#ifndef _RISCV_COP0_H
#define _RISCV_COP0_H
#include "config.h"
#define SR_ET 0x0000000000000001
#define SR_EF 0x0000000000000002
#define SR_EV 0x0000000000000004
@ -12,6 +10,9 @@
#define SR_UX 0x0000000000000040
#define SR_SX 0x0000000000000080
#define SR_IM 0x000000000000FF00
#define SR_VM 0x0000000000010000
#define SR_IM_SHIFT 8
#define PCR_SR 0
#define PCR_EPC 1
@ -20,32 +21,24 @@
#define PCR_COUNT 4
#define PCR_COMPARE 5
#define PCR_CAUSE 6
#define PCR_MEMSIZE 8
#define PCR_PTBR 7
#define PCR_SEND_IPI 8
#define PCR_CLR_IPI 9
#define PCR_COREID 10
#define PCR_K0 12
#define PCR_K1 13
#define PCR_TOHOST 16
#define PCR_FROMHOST 17
#define PCR_CONSOLE 18
#define PCR_K0 24
#define PCR_K1 25
#define CR_FSR 0
#define CR_TID 29
#define MEMSIZE_SHIFT 12
#define TIMER_PERIOD 0x1000
#define IPI_IRQ 5
#define TIMER_IRQ 7
#define CAUSE_EXCCODE 0x000000FF
#define CAUSE_IP 0x0000FF00
#define CAUSE_EXCCODE_SHIFT 0
#define CAUSE_IP_SHIFT 8
#define CAUSE_MISALIGNED_FETCH 0
#define CAUSE_FAULT_FETCH 1
#define CAUSE_ILLEGAL_INSTRUCTION 2
#define CAUSE_PRIVILEGED_INSTRUCTION 3
#define CAUSE_FP_DISABLED 4
#define CAUSE_INTERRUPT 5
#define CAUSE_SYSCALL 6
#define CAUSE_BREAKPOINT 7
#define CAUSE_MISALIGNED_LOAD 8
@ -55,25 +48,26 @@
#define CAUSE_VECTOR_DISABLED 12
#define CAUSE_VECTOR_BANK 13
#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 14
#define NUM_CAUSES 15
#define CAUSE_IRQ0 16
#define CAUSE_IRQ1 17
#define CAUSE_IRQ2 18
#define CAUSE_IRQ3 19
#define CAUSE_IRQ4 20
#define CAUSE_IRQ5 21
#define CAUSE_IRQ6 22
#define CAUSE_IRQ7 23
#define NUM_CAUSES 24
#define ASM_CR(r) _ASM_CR(r)
#define _ASM_CR(r) $cr##r
#define _ASM_CR(r) cr##r
#ifndef __ASSEMBLER__
#define mtpcr(reg,val) ({ long __tmp = (long)(val); \
asm volatile ("mtpcr %0,$cr%1"::"r"(__tmp),"i"(reg)); })
asm volatile ("mtpcr %0,cr%1"::"r"(__tmp),"i"(reg)); })
#define mfpcr(reg) ({ long __tmp; \
asm volatile ("mfpcr %0,$cr%1" : "=r"(__tmp) : "i"(reg)); \
__tmp; })
#define mtcr(reg,val) ({ long __tmp = (long)(val); \
asm volatile ("mtcr %0,$cr%1"::"r"(__tmp),"i"(reg)); })
#define mfcr(reg) ({ long __tmp; \
asm volatile ("mfcr %0,$cr%1" : "=r"(__tmp) : "i"(reg)); \
asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
__tmp; })
#define irq_disable() asm volatile("di")

12
pk/pk.c
View File

@ -164,14 +164,20 @@ static void jump_usrstart(const char* fn, long sp)
pop_tf(&tf);
}
uint32_t mem_mb;
void boot()
{
bss_init();
file_init();
long stack_top = (mfpcr(PCR_MEMSIZE) << MEMSIZE_SHIFT);
if(stack_top >= 0x80000000)
stack_top = 0x80000000;
// word 0 of memory contains # of MB of memory
mem_mb = *(uint32_t*)0;
unsigned long stack_top = 0x80000000;
if (mem_mb < stack_top / (1024 * 1024))
stack_top = mem_mb * (1024 * 1024);
stack_top -= USER_MAINVARS_SIZE;
struct args* args = mainvars_init(stack_top);

1
pk/pk.h
View File

@ -28,6 +28,7 @@ extern "C" {
extern int have_fp;
extern int have_vector;
extern uint32_t mem_mb;
int emulate_fp(trapframe_t*);
void init_fp(trapframe_t* tf);

26
pk/pk.ld
View File

@ -1,6 +1,6 @@
OUTPUT_ARCH( "mips:riscv" )
OUTPUT_ARCH( "riscv" )
ENTRY( __start )
ENTRY( _start )
SECTIONS
{
@ -10,7 +10,7 @@ SECTIONS
/*--------------------------------------------------------------------*/
/* Begining of code and text segment */
. = 0x00000000;
. = 0x00002000;
_ftext = .;
PROVIDE( eprol = . );
@ -56,18 +56,6 @@ SECTIONS
*(.gnu.linkonce.d.*)
}
/* lit4: Single precision floating point constants created by gas */
.lit4 :
{
*(.lit4)
}
/* lit8: Double precision floating point constants created by gas */
.lit8 :
{
*(.lit8)
}
/* End of initialized data segment */
. = ALIGN(4);
PROVIDE( edata = . );
@ -83,14 +71,6 @@ SECTIONS
/* sbss: Uninitialized writeable small data section */
. = .;
_sbss_start = .;
.sbss :
{
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
}
/* bss: Uninitialized writeable data section */
. = .;

6
pk/riscv-opc.h
View File

@ -124,13 +124,13 @@
#define MATCH_VSSEGSTB 0x80f
#define MASK_VSSEGSTB 0xfff
#define MATCH_MFTX_D 0x1c0d3
#define MASK_MFTX_D 0x7c1ffff
#define MASK_MFTX_D 0x3fffff
#define MATCH_DIV 0x633
#define MASK_DIV 0x1ffff
#define MATCH_C_LD 0x9
#define MASK_C_LD 0x1f
#define MATCH_MFTX_S 0x1c053
#define MASK_MFTX_S 0x7c1ffff
#define MASK_MFTX_S 0x3fffff
#define MATCH_VSSEGSTH 0x88f
#define MASK_VSSEGSTH 0xfff
#define MATCH_VVCFGIVL 0xf3
@ -154,7 +154,7 @@
#define MATCH_VSB 0xf
#define MASK_VSB 0x3fffff
#define MATCH_MFFSR 0x1d053
#define MASK_MFFSR 0x7ffffff
#define MASK_MFFSR 0x3fffff
#define MATCH_FDIV_S 0x3053
#define MASK_FDIV_S 0x1f1ff
#define MATCH_VLSTBU 0x120b

48
pk/riscv-pk.S
View File

@ -2,37 +2,33 @@
#include "pk.h"
.section .text,"ax",@progbits
.globl __start
.ent __start
__start:
.globl _start
.ent _start
_start:
lui $sp, %hi(stack_top)
add $sp, $sp, %lo(stack_top)
lui sp, %hi(stack_top)
add sp, sp, %lo(stack_top)
lui $t0, %hi(trap_entry)
add $t0, $t0, %lo(trap_entry)
mtpcr $t0, ASM_CR(PCR_EVEC)
lui t0, %hi(trap_entry)
add t0, t0, %lo(trap_entry)
mtpcr t0, ASM_CR(PCR_EVEC)
mtpcr $x0, ASM_CR(PCR_COUNT)
li $t0, TIMER_PERIOD
mtpcr $t0, ASM_CR(PCR_COMPARE)
li $t0, SR_S | SR_PS | SR_ET | SR_EC | SR_SX
or $t1, $t0, SR_EF | SR_EV
mtpcr $t1, ASM_CR(PCR_SR)
mfpcr $t1, ASM_CR(PCR_SR)
mtpcr $t0, ASM_CR(PCR_SR)
li t0, SR_S | SR_PS | SR_ET | SR_EC | SR_SX
or t1, t0, SR_EF | SR_EV
mtpcr t1, ASM_CR(PCR_SR)
mfpcr t1, ASM_CR(PCR_SR)
mtpcr t0, ASM_CR(PCR_SR)
and $t2, $t1, SR_EF
lui $t0, %hi(have_fp)
sw $t2, %lo(have_fp)($t0)
and t2, t1, SR_EF
lui t0, %hi(have_fp)
sw t2, %lo(have_fp)(t0)
and $t2, $t1, SR_EV
lui $t0, %hi(have_vector)
sw $t2, %lo(have_vector)($t0)
and t2, t1, SR_EV
lui t0, %hi(have_vector)
sw t2, %lo(have_vector)(t0)
lui $t0, %hi(boot)
jalr.j $t0, %lo(boot)
lui t0, %hi(boot)
jalr.j t0, %lo(boot)
#j boot
.end __start
.end _start

2
pk/syscall.c
View File

@ -95,7 +95,7 @@ sysret_t sys_unlink(const char* name, size_t len)
sysret_t sys_brk(size_t pos)
{
if(pos > (mfpcr(PCR_MEMSIZE) << MEMSIZE_SHIFT))
if(pos / (1024 * 1024) >= mem_mb)
return (sysret_t){-1, ENOMEM};
return (sysret_t){0,0};
}

Write Preview
Loading…
Cancel
Save