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Changes to allow spike & RTL behavior to better match each other.

- EI turned off on sys_exit.
  - IM/IP cleared on start.
  - badvaddr only saved to tf on page faults.
pull/2/head
Christopher Celio 12 years ago
parent
commit
7b6a968c83
  1. 2
      pk/entry.S
  2. 2
      pk/handlers.c
  3. 8
      pk/pk.S
  4. 1
      pk/syscall.c

2
pk/entry.S

@ -49,13 +49,11 @@
csrr x4,sup1 # x2
csrr x5,status
csrr x6,epc
csrr x7,badvaddr
csrr x8,cause
STORE x3,1*REGBYTES(x2)
STORE x4,2*REGBYTES(x2)
STORE x5,32*REGBYTES(x2)
STORE x6,33*REGBYTES(x2)
STORE x7,34*REGBYTES(x2)
STORE x8,35*REGBYTES(x2)
la gp, _gp

2
pk/handlers.c

@ -98,12 +98,14 @@ static void handle_fault_fetch(trapframe_t* tf)
void handle_fault_load(trapframe_t* tf)
{
tf->badvaddr = read_csr(badvaddr);
if (handle_page_fault(tf->badvaddr, PROT_READ) != 0)
segfault(tf, tf->badvaddr, "load");
}
void handle_fault_store(trapframe_t* tf)
{
tf->badvaddr = read_csr(badvaddr);
if (handle_page_fault(tf->badvaddr, PROT_WRITE) != 0)
segfault(tf, tf->badvaddr, "store");
}

8
pk/pk.S

@ -11,7 +11,13 @@ _start:
la gp, _gp
csrw evec, a0
li a0, SR_S | SR_PS | SR_EI | SR_S64
# clear any pending interrupts
li t0, -1
csrw compare, t0
csrw count,zero
csrwi clear_ipi, 0
li a0, SR_S | SR_PS | SR_EI | SR_S64 | SR_U64
or a1, a0, SR_EF | SR_EA
csrw status, a1
csrr a1, status

1
pk/syscall.c

@ -28,6 +28,7 @@ void sys_exit(int code)
printk("%ld cycles\n", rdcycle() - current.t0);
frontend_syscall(SYS_exit, code, 0, 0, 0, 0);
clear_csr(status, SR_EI);
while (1);
}

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