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[sim,xcc,pk,opcodes] static rounding modes for FP insns 

Now, you can either use the RM in the FSR or specify it in the insn.

(Except for FP->int; no dynamic for that.)
cs250
Andrew Waterman 16 years ago
parent
f415fce416
commit
6ba19295c0
2 changed files with 113 additions and 38 deletions
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  1. 41
      pk/fp.c
  2. 110
      pk/riscv-opc.h

41
pk/fp.c
View File

@ -36,6 +36,7 @@ int emulate_fp(trapframe_t* tf)
#define RRS3 ((tf->insn >> 5) & 0x1F)
#define RRDR ( tf->insn & 0x1F)
#define RRDI RRS2
#define RM ((tf->insn >> 11) & 0x3)
#define IMM (((int32_t)tf->insn << 20) >> 20)
@ -171,22 +172,46 @@ int emulate_fp(trapframe_t* tf)
set_fp_reg(RRDR, 0, f32_sqrt(frs1s));
else if(IS_INSN(SQRT_D))
set_fp_reg(RRDR, 1, f64_sqrt(frs1d));
else if(IS_INSN(TRUNC_W_S))
else if(IS_INSN(CVT_W_S_RM))
{
softfloat_roundingMode = RM;
XRDR = f32_to_i32_r_minMag(frs1s,true);
else if(IS_INSN(TRUNC_W_D))
}
else if(IS_INSN(CVT_W_D_RM))
{
softfloat_roundingMode = RM;
XRDR = f64_to_i32_r_minMag(frs1d,true);
else if(IS_INSN(TRUNC_L_S))
}
else if(IS_INSN(CVT_L_S_RM))
{
softfloat_roundingMode = RM;
XRDR = f32_to_i64_r_minMag(frs1s,true);
else if(IS_INSN(TRUNC_L_D))
}
else if(IS_INSN(CVT_L_D_RM))
{
softfloat_roundingMode = RM;
XRDR = f64_to_i64_r_minMag(frs1d,true);
else if(IS_INSN(TRUNCU_W_S))
}
else if(IS_INSN(CVTU_W_S_RM))
{
softfloat_roundingMode = RM;
XRDR = f32_to_ui32_r_minMag(frs1s,true);
else if(IS_INSN(TRUNCU_W_D))
}
else if(IS_INSN(CVTU_W_D_RM))
{
softfloat_roundingMode = RM;
XRDR = f64_to_ui32_r_minMag(frs1d,true);
else if(IS_INSN(TRUNCU_L_S))
}
else if(IS_INSN(CVTU_L_S_RM))
{
softfloat_roundingMode = RM;
XRDR = f32_to_ui64_r_minMag(frs1s,true);
else if(IS_INSN(TRUNCU_L_D))
}
else if(IS_INSN(CVTU_L_D_RM))
{
softfloat_roundingMode = RM;
XRDR = f64_to_ui64_r_minMag(frs1d,true);
}
else
return -1;

110
pk/riscv-opc.h
View File

@ -5,9 +5,11 @@
#define MASK_SGNINJ_D 0xfe007fe0
#define MATCH_AMO_ADD 0xf4003000
#define MASK_AMO_ADD 0xfe007fe0
#define MATCH_CVT_D_L_RM 0xd4006580
#define MASK_CVT_D_L_RM 0xfff067e0
#define MATCH_REMUW 0xee0010e0
#define MASK_REMUW 0xfe007fe0
#define MATCH_NMADD_S 0xd6000c00
#define MATCH_NMADD_S 0xde000000
#define MASK_NMADD_S 0xfe007c00
#define MATCH_BLTU 0xe6006000
#define MASK_BLTU 0xfe007000
@ -19,7 +21,9 @@
#define MASK_DIV_D 0xfe007fe0
#define MATCH_CVT_S_W 0xd40001c0
#define MASK_CVT_S_W 0xfff07fe0
#define MATCH_NMADD_D 0xd6006c00
#define MATCH_CVTU_S_W_RM 0xd40005e0
#define MASK_CVTU_S_W_RM 0xfff067e0
#define MATCH_NMADD_D 0xde006000
#define MASK_NMADD_D 0xfe007c00
#define MATCH_C_EQ_D 0xd40062a0
#define MASK_C_EQ_D 0xfe007fe0
@ -27,22 +31,24 @@
#define MASK_SLLIW 0xfe007fe0
#define MATCH_LB 0xf0000000
#define MASK_LB 0xfe007000
#define MATCH_CVT_L_S_RM 0xd4000500
#define MASK_CVT_L_S_RM 0xfff067e0
#define MATCH_CVTU_D_L 0xd40061a0
#define MASK_CVTU_D_L 0xfff07fe0
#define MATCH_TRUNC_W_D 0xd4006140
#define MASK_TRUNC_W_D 0xfff07fe0
#define MATCH_LH 0xf0001000
#define MASK_LH 0xfe007000
#define MATCH_MSUB_S_RM 0xda000400
#define MASK_MSUB_S_RM 0xfe006400
#define MATCH_LW 0xf0002000
#define MASK_LW 0xfe007000
#define MATCH_ADD 0xea000000
#define MASK_ADD 0xfe007fe0
#define MATCH_CVT_W_D_RM 0xd4006540
#define MASK_CVT_W_D_RM 0xfff067e0
#define MATCH_AMOW_AND 0xf4002040
#define MASK_AMOW_AND 0xfe007fe0
#define MATCH_MFPCR 0xfc004000
#define MASK_MFPCR 0xfe0fffe0
#define MATCH_TRUNC_W_S 0xd4000140
#define MASK_TRUNC_W_S 0xfff07fe0
#define MATCH_CVTU_D_W 0xd40061e0
#define MASK_CVTU_D_W 0xfff07fe0
#define MATCH_BNE 0xe6001000
@ -59,6 +65,8 @@
#define MASK_SLTIU 0xfe007000
#define MATCH_MFFL_D 0xd4006b20
#define MASK_MFFL_D 0xfe0fffe0
#define MATCH_MADD_S_RM 0xd8000400
#define MASK_MADD_S_RM 0xfe006400
#define MATCH_BREAK 0xf6006000
#define MASK_BREAK 0xfffff000
#define MATCH_ADD_D 0xd4006000
@ -69,10 +77,14 @@
#define MASK_AMOW_MIN 0xfe007fe0
#define MATCH_NOR 0xea0000e0
#define MASK_NOR 0xfe007fe0
#define MATCH_NMSUB_D 0xd6006800
#define MATCH_NMSUB_D 0xdc006000
#define MASK_NMSUB_D 0xfe007c00
#define MATCH_AMO_SWAP 0xf4003020
#define MASK_AMO_SWAP 0xfe007fe0
#define MATCH_CVTU_S_L_RM 0xd40005a0
#define MASK_CVTU_S_L_RM 0xfff067e0
#define MATCH_MADD_D_RM 0xd8006400
#define MASK_MADD_D_RM 0xfe006400
#define MATCH_SRLI 0xe8007080
#define MASK_SRLI 0xfe007fc0
#define MATCH_DIVUW 0xee0010a0
@ -81,7 +93,7 @@
#define MASK_MFFH_D 0xfe0fffe0
#define MATCH_SRLW 0xee007080
#define MASK_SRLW 0xfe007fe0
#define MATCH_NMSUB_S 0xd6000800
#define MATCH_NMSUB_S 0xdc000000
#define MASK_NMSUB_S 0xfe007c00
#define MATCH_MFCR 0xf6002000
#define MASK_MFCR 0xfe0fffe0
@ -101,11 +113,13 @@
#define MASK_SYNC 0xffffffff
#define MATCH_MTF_S 0xd4000b80
#define MASK_MTF_S 0xfff07fe0
#define MATCH_CVTU_W_D_RM 0xd4006560
#define MASK_CVTU_W_D_RM 0xfff067e0
#define MATCH_S_S 0xd2002000
#define MASK_S_S 0xfe007000
#define MATCH_MTCR 0xf6003000
#define MASK_MTCR 0xfe007fff
#define MATCH_MSUB_S 0xd6000400
#define MATCH_MSUB_S 0xda000000
#define MASK_MSUB_S 0xfe007c00
#define MATCH_ADDW 0xee000000
#define MASK_ADDW 0xfe007fe0
@ -117,6 +131,8 @@
#define MASK_SUB 0xfe007fe0
#define MATCH_ERET 0xfc002000
#define MASK_ERET 0xffffffff
#define MATCH_SQRT_D_RM 0xd4006480
#define MASK_SQRT_D_RM 0xfff067e0
#define MATCH_BLT 0xe6004000
#define MASK_BLT 0xfe007000
#define MATCH_SGNINJN_D 0xd40060c0
@ -127,8 +143,12 @@
#define MASK_SRLIW 0xfe007fe0
#define MATCH_LUI 0xe2000000
#define MASK_LUI 0xfe000000
#define MATCH_CVTU_D_L_RM 0xd40065a0
#define MASK_CVTU_D_L_RM 0xfff067e0
#define MATCH_ADDI 0xe8000000
#define MASK_ADDI 0xfe007000
#define MATCH_ADD_D_RM 0xd4006400
#define MASK_ADD_D_RM 0xfe0067e0
#define MATCH_MULH 0xea001040
#define MASK_MULH 0xfe007fe0
#define MATCH_MULHUW 0xee001060
@ -143,6 +163,8 @@
#define MASK_LD 0xfe007000
#define MATCH_ORI 0xe8005000
#define MASK_ORI 0xfe007000
#define MATCH_CVT_L_D_RM 0xd4006500
#define MASK_CVT_L_D_RM 0xfff067e0
#define MATCH_AMOW_MAX 0xf40020a0
#define MASK_AMOW_MAX 0xfe007fe0
#define MATCH_ADDIW 0xec000000
@ -151,22 +173,26 @@
#define MASK_MULW 0xfe007fe0
#define MATCH_MTFLH_D 0xd4006f80
#define MASK_MTFLH_D 0xfe007fe0
#define MATCH_CVT_D_S 0xd4006600
#define MASK_CVT_D_S 0xfff07fe0
#define MATCH_MUL_S_RM 0xd4000440
#define MASK_MUL_S_RM 0xfe0067e0
#define MATCH_SRA 0xea0070c0
#define MASK_SRA 0xfe007fe0
#define MATCH_TRUNC_L_S 0xd4000100
#define MASK_TRUNC_L_S 0xfff07fe0
#define MATCH_BGE 0xe6005000
#define MASK_BGE 0xfe007000
#define MATCH_SRAIW 0xec0070c0
#define MASK_SRAIW 0xfe007fe0
#define MATCH_SRL 0xea007080
#define MASK_SRL 0xfe007fe0
#define MATCH_TRUNC_L_D 0xd4006100
#define MASK_TRUNC_L_D 0xfff07fe0
#define MATCH_CVTU_L_S_RM 0xd4000520
#define MASK_CVTU_L_S_RM 0xfff067e0
#define MATCH_NMSUB_D_RM 0xdc006400
#define MASK_NMSUB_D_RM 0xfe006400
#define MATCH_NMSUB_S_RM 0xdc000400
#define MASK_NMSUB_S_RM 0xfe006400
#define MATCH_OR 0xea0000a0
#define MASK_OR 0xfe007fe0
#define MATCH_CVT_S_W_RM 0xd40005c0
#define MASK_CVT_S_W_RM 0xfff067e0
#define MATCH_SUBW 0xee000020
#define MASK_SUBW 0xfe007fe0
#define MATCH_JALR_C 0xf6000000
@ -179,16 +205,14 @@
#define MASK_JALR_J 0xfff07fe0
#define MATCH_S_D 0xd2003000
#define MASK_S_D 0xfe007000
#define MATCH_TRUNCU_L_S 0xd4000120
#define MASK_TRUNCU_L_S 0xfff07fe0
#define MATCH_AMO_OR 0xf4003060
#define MASK_AMO_OR 0xfe007fe0
#define MATCH_XORI 0xe8006000
#define MASK_XORI 0xfe007000
#define MATCH_JALR_R 0xf6000020
#define MASK_JALR_R 0xfff07fe0
#define MATCH_TRUNCU_L_D 0xd4006120
#define MASK_TRUNCU_L_D 0xfff07fe0
#define MATCH_NMADD_S_RM 0xde000400
#define MASK_NMADD_S_RM 0xfe006400
#define MATCH_CVTU_S_L 0xd40001a0
#define MASK_CVTU_S_L 0xfff07fe0
#define MATCH_AMO_MAX 0xf40030a0
@ -197,16 +221,30 @@
#define MASK_AMO_MIN 0xfe007fe0
#define MATCH_ANDI 0xe8004000
#define MASK_ANDI 0xfe007000
#define MATCH_SQRT_S_RM 0xd4000480
#define MASK_SQRT_S_RM 0xfff067e0
#define MATCH_CVTU_L_D_RM 0xd4006520
#define MASK_CVTU_L_D_RM 0xfff067e0
#define MATCH_JAL 0xc8000000
#define MASK_JAL 0xf8000000
#define MATCH_LWU 0xf0006000
#define MASK_LWU 0xfe007000
#define MATCH_CVT_S_D_RM 0xd4000660
#define MASK_CVT_S_D_RM 0xfff067e0
#define MATCH_AMO_MINU 0xf40030c0
#define MASK_AMO_MINU 0xfe007fe0
#define MATCH_MSUB_D 0xd6006400
#define MASK_MSUB_D 0xfe007c00
#define MATCH_SUB_S_RM 0xd4000420
#define MASK_SUB_S_RM 0xfe0067e0
#define MATCH_CVT_S_L 0xd4000180
#define MASK_CVT_S_L 0xfff07fe0
#define MATCH_DIV_S_RM 0xd4000460
#define MASK_DIV_S_RM 0xfe0067e0
#define MATCH_MUL_D_RM 0xd4006440
#define MASK_MUL_D_RM 0xfe0067e0
#define MATCH_SUB_S 0xd4000020
#define MASK_SUB_S 0xfe007fe0
#define MATCH_NMADD_D_RM 0xde006400
#define MASK_NMADD_D_RM 0xfe006400
#define MATCH_SLT 0xea000040
#define MASK_SLT 0xfe007fe0
#define MATCH_SLLW 0xee007040
@ -225,6 +263,8 @@
#define MASK_SLLI 0xfe007fc0
#define MATCH_SUB_D 0xd4006020
#define MASK_SUB_D 0xfe007fe0
#define MATCH_CVT_S_L_RM 0xd4000580
#define MASK_CVT_S_L_RM 0xfff067e0
#define MATCH_BEQ 0xe6000000
#define MASK_BEQ 0xfe007000
#define MATCH_AND 0xea000080
@ -241,23 +281,27 @@
#define MASK_MTF_D 0xfff07fe0
#define MATCH_SQRT_D 0xd4006080
#define MASK_SQRT_D 0xfff07fe0
#define MATCH_ADD_S_RM 0xd4000400
#define MASK_ADD_S_RM 0xfe0067e0
#define MATCH_AMOW_ADD 0xf4002000
#define MASK_AMOW_ADD 0xfe007fe0
#define MATCH_MULHW 0xee001040
#define MASK_MULHW 0xfe007fe0
#define MATCH_MADD_S 0xd6000000
#define MATCH_MADD_S 0xd8000000
#define MASK_MADD_S 0xfe007c00
#define MATCH_MULHU 0xea001060
#define MASK_MULHU 0xfe007fe0
#define MATCH_AMO_AND 0xf4003040
#define MASK_AMO_AND 0xfe007fe0
#define MATCH_MSUB_D 0xda006000
#define MASK_MSUB_D 0xfe007c00
#define MATCH_SGNMUL_S 0xd40000e0
#define MASK_SGNMUL_S 0xfe007fe0
#define MATCH_RDNPC 0xf6001000
#define MASK_RDNPC 0xffffffe0
#define MATCH_CVT_S_L 0xd4000180
#define MASK_CVT_S_L 0xfff07fe0
#define MATCH_MADD_D 0xd6006000
#define MATCH_DIV_D_RM 0xd4006460
#define MASK_DIV_D_RM 0xfe0067e0
#define MATCH_MADD_D 0xd8006000
#define MASK_MADD_D 0xfe007c00
#define MATCH_SYNCI 0xf0007000
#define MASK_SYNCI 0xfff07000
@ -265,14 +309,16 @@
#define MASK_DIV_S 0xfe007fe0
#define MATCH_UNIMP 0x0
#define MASK_UNIMP 0xffffffff
#define MATCH_CVT_S_D 0xd4000660
#define MATCH_CVT_S_D 0xd4000260
#define MASK_CVT_S_D 0xfff07fe0
#define MATCH_C_LE_S 0xd40002e0
#define MASK_C_LE_S 0xfe007fe0
#define MATCH_MUL_S 0xd4000040
#define MASK_MUL_S 0xfe007fe0
#define MATCH_TRUNCU_W_S 0xd4000160
#define MASK_TRUNCU_W_S 0xfff07fe0
#define MATCH_CVT_W_S_RM 0xd4000540
#define MASK_CVT_W_S_RM 0xfff067e0
#define MATCH_CVT_D_S 0xd4006200
#define MASK_CVT_D_S 0xfff07fe0
#define MATCH_CVT_D_W 0xd40061c0
#define MASK_CVT_D_W 0xfff07fe0
#define MATCH_L_S 0xd0002000
@ -285,10 +331,10 @@
#define MASK_L_D 0xfe007000
#define MATCH_DIVU 0xea0010a0
#define MASK_DIVU 0xfe007fe0
#define MATCH_TRUNCU_W_D 0xd4006160
#define MASK_TRUNCU_W_D 0xfff07fe0
#define MATCH_MUL_D 0xd4006040
#define MASK_MUL_D 0xfe007fe0
#define MATCH_MSUB_D_RM 0xda006400
#define MASK_MSUB_D_RM 0xfe006400
#define MATCH_SW 0xf2002000
#define MASK_SW 0xfe007000
#define MATCH_AMOW_SWAP 0xf4002020
@ -305,5 +351,9 @@
#define MASK_SB 0xfe007000
#define MATCH_C_LT_D 0xd40062c0
#define MASK_C_LT_D 0xfe007fe0
#define MATCH_CVTU_W_S_RM 0xd4000560
#define MASK_CVTU_W_S_RM 0xfff067e0
#define MATCH_SUB_D_RM 0xd4006420
#define MASK_SUB_D_RM 0xfe0067e0
#define MATCH_SD 0xf2003000
#define MASK_SD 0xfe007000

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