implement new register mapping

pk/entry.S

@@ -76,13 +76,14 @@ save_tf:  # write the trap frame onto the stack
   .globl  pop_tf
 pop_tf:  # write the trap frame onto the stack
   # restore gprs
-  LOAD  t0,32*REGBYTES(a0)  # restore sr (should disable interrupts)
-  mtpcr  t0,ASM_CR(PCR_SR)
+  LOAD  a1,32*REGBYTES(a0)
+  LOAD  a2,1*REGBYTES(a0)
+  LOAD  a3,2*REGBYTES(a0)
+
+  mtpcr  a1,ASM_CR(PCR_SR) # restore sr (disable interrupts)
+  mtpcr  a2,ASM_CR(PCR_K0)
+  mtpcr a3,ASM_CR(PCR_K1)
 
-  LOAD  x1,1*REGBYTES(a0)
-  mtpcr  x1,ASM_CR(PCR_K0)
-  LOAD  x1,2*REGBYTES(a0)
-  mtpcr x1,ASM_CR(PCR_K1)
   move  x1,a0
   LOAD  x3,3*REGBYTES(x1)
   LOAD  x4,4*REGBYTES(x1)

pk/handlers.c

@@ -110,11 +110,11 @@ static void handle_syscall(trapframe_t* tf)
 {
   setpcr(PCR_SR, SR_ET);
 
-  long n = tf->gpr[2];
-  sysret_t ret = syscall(tf->gpr[4], tf->gpr[5], tf->gpr[6], tf->gpr[7], n);
+  long n = tf->gpr[16];
+  sysret_t ret = syscall(tf->gpr[18], tf->gpr[19], tf->gpr[20], tf->gpr[21], n);
 
-  tf->gpr[2] = ret.result;
-  tf->gpr[3] = ret.result == -1 ? ret.err : 0;
+  tf->gpr[16] = ret.result;
+  tf->gpr[17] = ret.result == -1 ? ret.err : 0;
 
   advance_pc(tf);
 }

pk/init.c

@@ -107,10 +107,10 @@ void sprintk(char* out, const char* s, ...)
 void dump_tf(trapframe_t* tf)
 {
   static const char* regnames[] = {
-    "z ", "ra", "v0", "v1", "a0", "a1", "a2", "a3",
-    "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
-    "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3",
-    "s4", "s5", "s6", "s7", "s8", "fp", "sp", "tp"
+    "z ", "ra", "s0", "s1", "s2", "s3", "s4", "s5",
+    "s6", "s7", "s8", "s9", "sA", "sB", "sp", "tp",
+    "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5",
+    "a6", "a7", "a8", "a9", "aA", "aB", "aC", "aD"
   };
 
   tf->gpr[0] = 0;
@@ -132,7 +132,7 @@ void init_tf(trapframe_t* tf, long pc, long sp, int user64)
   tf->sr = (mfpcr(PCR_SR) & (SR_IM | SR_S64)) | SR_S | SR_EC;
   if(user64)
     tf->sr |= SR_U64;
-  tf->gpr[30] = sp;
+  tf->gpr[14] = sp;
   tf->epc = pc;
 }
 

pk/pk.S

@@ -10,28 +10,28 @@ _start:
   lui sp, %hi(stack_top)
   add sp, sp, %lo(stack_top)
 
-  lui t0, %hi(trap_entry)
-  add t0, t0, %lo(trap_entry)
-  mtpcr t0, ASM_CR(PCR_EVEC)
+  lui a0, %hi(trap_entry)
+  add a0, a0, %lo(trap_entry)
+  mtpcr a0, ASM_CR(PCR_EVEC)
 
 #ifdef __riscv64
-  li t0, SR_S | SR_PS | SR_ET | SR_EC | SR_S64
+  li a0, SR_S | SR_PS | SR_ET | SR_EC | SR_S64
 #else
-  li t0, SR_S | SR_PS | SR_ET | SR_EC
+  li a0, SR_S | SR_PS | SR_ET | SR_EC
 #endif
-  or t1, t0, SR_EF | SR_EV
-  mtpcr t1, ASM_CR(PCR_SR)
-  mfpcr t1, ASM_CR(PCR_SR)
-  mtpcr t0, ASM_CR(PCR_SR)
+  or a1, a0, SR_EF | SR_EV
+  mtpcr a1, ASM_CR(PCR_SR)
+  mfpcr a1, ASM_CR(PCR_SR)
+  mtpcr a0, ASM_CR(PCR_SR)
   
-  and t2, t1, SR_EF
-  lui t0, %hi(have_fp)
-  sw  t2, %lo(have_fp)(t0)
+  and a2, a1, SR_EF
+  lui a0, %hi(have_fp)
+  sw  a2, %lo(have_fp)(a0)
   
-  and t2, t1, SR_EV
-  lui t0, %hi(have_vector)
-  sw  t2, %lo(have_vector)(t0)
+  and a2, a1, SR_EV
+  lui a0, %hi(have_vector)
+  sw  a2, %lo(have_vector)(a0)
 
-  lui t0, %hi(boot)
-  jalr.j t0, %lo(boot)
+  lui a0, %hi(boot)
+  jalr.j a0, %lo(boot)
   #j boot

pk/riscv-opc.h

@@ -1,5 +1,3 @@
-// See LICENSE for license details.
-
 /* Automatically generated by parse-opcodes */
 #define MATCH_MOVN 0x6f7
 #define  MASK_MOVN 0x1ffff
@@ -9,6 +7,8 @@
 #define  MASK_REMUW 0x1ffff
 #define MATCH_FMIN_D 0x180d3
 #define  MASK_FMIN_D 0x1ffff
+#define MATCH_LR_W 0x1012b
+#define  MASK_LR_W 0x3fffff
 #define MATCH_VLSTHU 0x128b
 #define  MASK_VLSTHU 0x1ffff
 #define MATCH_C_SWSP 0x8
@@ -21,8 +21,6 @@
 #define  MASK_VVCFG 0xf801ffff
 #define MATCH_MOVZ 0x2f7
 #define  MASK_MOVZ 0x1ffff
-#define MATCH_FCVT_LU_S 0x9053
-#define  MASK_FCVT_LU_S 0x3ff1ff
 #define MATCH_C_LD 0x9
 #define  MASK_C_LD 0x1f
 #define MATCH_C_SRLI32 0xc19
@@ -195,6 +193,8 @@
 #define  MASK_MTFSR 0x3fffff
 #define MATCH_VSSTH 0x108f
 #define  MASK_VSSTH 0x1ffff
+#define MATCH_SC_W 0x1052b
+#define  MASK_SC_W 0x1ffff
 #define MATCH_REM 0x733
 #define  MASK_REM 0x1ffff
 #define MATCH_SRLIW 0x29b
@@ -257,6 +257,8 @@
 #define  MASK_SRL 0x1ffff
 #define MATCH_VENQCMD 0x2b7b
 #define  MASK_VENQCMD 0xf801ffff
+#define MATCH_FSUB_D 0x10d3
+#define  MASK_FSUB_D 0x1f1ff
 #define MATCH_VFMTS 0x1973
 #define  MASK_VFMTS 0x1ffff
 #define MATCH_VENQIMM1 0x2f7b
@@ -343,8 +345,8 @@
 #define  MASK_AMOADD_D 0x1ffff
 #define MATCH_C_SW 0xd
 #define  MASK_C_SW 0x1f
-#define MATCH_AMOMAX_W 0x152b
-#define  MASK_AMOMAX_W 0x1ffff
+#define MATCH_LR_D 0x101ab
+#define  MASK_LR_D 0x3fffff
 #define MATCH_C_MOVE 0x2
 #define  MASK_C_MOVE 0x801f
 #define MATCH_FMOVN 0xef7
@@ -449,6 +451,8 @@
 #define  MASK_VFLSEGW 0x1ffff
 #define MATCH_VLSEGSTH 0x88b
 #define  MASK_VLSEGSTH 0xfff
+#define MATCH_AMOMAX_W 0x152b
+#define  MASK_AMOMAX_W 0x1ffff
 #define MATCH_FSGNJ_D 0x50d3
 #define  MASK_FSGNJ_D 0x1ffff
 #define MATCH_VFLSEGSTW 0xd0b
@@ -465,22 +469,24 @@
 #define  MASK_VMST 0x1ffff
 #define MATCH_SETPCR 0xfb
 #define  MASK_SETPCR 0x3ff
-#define MATCH_RDNPC 0x26b
-#define  MASK_RDNPC 0x7ffffff
+#define MATCH_FCVT_LU_S 0x9053
+#define  MASK_FCVT_LU_S 0x3ff1ff
 #define MATCH_VXCPTHOLD 0x277b
 #define  MASK_VXCPTHOLD 0xffffffff
 #define MATCH_FCVT_S_L 0xc053
 #define  MASK_FCVT_S_L 0x3ff1ff
 #define MATCH_VFLSEGSTD 0xd8b
 #define  MASK_VFLSEGSTD 0xfff
+#define MATCH_AUIPC 0x17
+#define  MASK_AUIPC 0x7f
 #define MATCH_C_ADD 0x1a
 #define  MASK_C_ADD 0x801f
 #define MATCH_FCVT_LU_D 0x90d3
 #define  MASK_FCVT_LU_D 0x3ff1ff
 #define MATCH_VFLD 0x58b
 #define  MASK_VFLD 0x3fffff
-#define MATCH_FSUB_D 0x10d3
-#define  MASK_FSUB_D 0x1f1ff
+#define MATCH_SC_D 0x105ab
+#define  MASK_SC_D 0x1ffff
 #define MATCH_FMADD_S 0x43
 #define  MASK_FMADD_S 0x1ff
 #define MATCH_FCVT_W_S 0xa053