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riscv-pk
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[xcc, sim, pk, opcodes] new instruction encoding!

cs250
Andrew Waterman 16 years ago
parent
4daccfc1cf
commit
16a55362ca
2 changed files with 388 additions and 388 deletions
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  1. 110
      pk/fp.c
  2. 666
      pk/riscv-opc.h

110
pk/fp.c
View File

@ -31,18 +31,19 @@ int emulate_fp(trapframe_t* tf)
if(noisy)
printk("FPU emulation at pc %lx, insn %x\n",tf->epc,(uint32_t)tf->insn);
#define RRS1 ((tf->insn >> 15) & 0x1F)
#define RRS2 ((tf->insn >> 20) & 0x1F)
#define RRS3 ((tf->insn >> 5) & 0x1F)
#define RRDR ( tf->insn & 0x1F)
#define RRDI RRS2
#define RM ((tf->insn >> 11) & 0x3)
#define RRS1 ((tf->insn >> 5) & 0x1F)
#define RRS2 ((tf->insn >> 10) & 0x1F)
#define RRS3 ((tf->insn >> 15) & 0x1F)
#define RRD ( tf->insn & 0x1F)
#define RM ((tf->insn >> 20) & 0x3)
#define IMM (((int32_t)tf->insn << 20) >> 20)
int32_t imm = ((int32_t)tf->insn << 10) >> 20;
int32_t bimm = (tf->insn & 0x1f) | (((tf->insn >> 15) & 0x7f) << 5);
bimm = (bimm << 20) >> 20;
#define XRS1 (tf->gpr[RRS1])
#define XRS2 (tf->gpr[RRS2])
#define XRDR (tf->gpr[RRDR])
#define XRDR (tf->gpr[RRD])
uint64_t frs1d = get_fp_reg(RRS1, 1);
uint64_t frs2d = get_fp_reg(RRS2, 1);
@ -51,7 +52,8 @@ int emulate_fp(trapframe_t* tf)
uint32_t frs2s = get_fp_reg(RRS2, 0);
uint32_t frs3s = get_fp_reg(RRS3, 0);
uint64_t effective_address = XRS1 + IMM;
uint64_t effective_address_load = XRS1 + imm;
uint64_t effective_address_store = XRS1 + bimm;
softfloat_exceptionFlags = 0;
softfloat_roundingMode = (fp_state.fsr >> 5) & 3;
@ -60,23 +62,23 @@ int emulate_fp(trapframe_t* tf)
if(IS_INSN(L_S))
{
validate_address(tf, effective_address, 4, 0);
set_fp_reg(RRDI, 0, *(uint32_t*)effective_address);
validate_address(tf, effective_address_load, 4, 0);
set_fp_reg(RRD, 0, *(uint32_t*)effective_address_load);
}
else if(IS_INSN(L_D))
{
validate_address(tf, effective_address, 8, 0);
set_fp_reg(RRDI, 1, *(uint64_t*)effective_address);
validate_address(tf, effective_address_load, 8, 0);
set_fp_reg(RRD, 1, *(uint64_t*)effective_address_load);
}
else if(IS_INSN(S_S))
{
validate_address(tf, effective_address, 4, 1);
*(uint32_t*)effective_address = frs2s;
validate_address(tf, effective_address_store, 4, 1);
*(uint32_t*)effective_address_store = frs2s;
}
else if(IS_INSN(S_D))
{
validate_address(tf, effective_address, 8, 1);
*(uint64_t*)effective_address = frs2d;
validate_address(tf, effective_address_store, 8, 1);
*(uint64_t*)effective_address_store = frs2d;
}
else if(IS_INSN(MFF_S))
XRDR = frs2s;
@ -87,23 +89,23 @@ int emulate_fp(trapframe_t* tf)
else if(IS_INSN(MFFH_D))
XRDR = (int64_t)frs2d >> 32;
else if(IS_INSN(MTF_S))
set_fp_reg(RRDR, 0, XRS1);
set_fp_reg(RRD, 0, XRS1);
else if(IS_INSN(MTF_D))
set_fp_reg(RRDR, 1, XRS1);
set_fp_reg(RRD, 1, XRS1);
else if(IS_INSN(MTFLH_D))
set_fp_reg(RRDR, 1, (uint32_t)XRS1 | (XRS2 << 32));
set_fp_reg(RRD, 1, (uint32_t)XRS1 | (XRS2 << 32));
else if(IS_INSN(SGNINJ_S))
set_fp_reg(RRDR, 0, (frs1s &~ (uint32_t)INT32_MIN) | (frs2s & (uint32_t)INT32_MIN));
set_fp_reg(RRD, 0, (frs1s &~ (uint32_t)INT32_MIN) | (frs2s & (uint32_t)INT32_MIN));
else if(IS_INSN(SGNINJ_D))
set_fp_reg(RRDR, 1, (frs1d &~ INT64_MIN) | (frs2d & INT64_MIN));
set_fp_reg(RRD, 1, (frs1d &~ INT64_MIN) | (frs2d & INT64_MIN));
else if(IS_INSN(SGNINJN_S))
set_fp_reg(RRDR, 0, (frs1s &~ (uint32_t)INT32_MIN) | ((~frs2s) & (uint32_t)INT32_MIN));
set_fp_reg(RRD, 0, (frs1s &~ (uint32_t)INT32_MIN) | ((~frs2s) & (uint32_t)INT32_MIN));
else if(IS_INSN(SGNINJN_D))
set_fp_reg(RRDR, 1, (frs1d &~ INT64_MIN) | ((~frs2d) & INT64_MIN));
set_fp_reg(RRD, 1, (frs1d &~ INT64_MIN) | ((~frs2d) & INT64_MIN));
else if(IS_INSN(SGNMUL_S))
set_fp_reg(RRDR, 0, frs1s ^ (frs2s & (uint32_t)INT32_MIN));
set_fp_reg(RRD, 0, frs1s ^ (frs2s & (uint32_t)INT32_MIN));
else if(IS_INSN(SGNMUL_D))
set_fp_reg(RRDR, 1, frs1d ^ (frs2d & INT64_MIN));
set_fp_reg(RRD, 1, frs1d ^ (frs2d & INT64_MIN));
else if(IS_INSN(C_EQ_S))
XRDR = f32_eq(frs1s, frs2s);
else if(IS_INSN(C_EQ_D))
@ -117,61 +119,61 @@ int emulate_fp(trapframe_t* tf)
else if(IS_INSN(C_LT_D))
XRDR = f64_lt(frs1d, frs2d);
else if(IS_INSN(CVT_S_W))
set_fp_reg(RRDR, 0, i32_to_f32(XRS1));
set_fp_reg(RRD, 0, i32_to_f32(XRS1));
else if(IS_INSN(CVT_S_L))
set_fp_reg(RRDR, 0, i64_to_f32(XRS1));
set_fp_reg(RRD, 0, i64_to_f32(XRS1));
else if(IS_INSN(CVT_S_D))
set_fp_reg(RRDR, 0, f64_to_f32(frs1d));
set_fp_reg(RRD, 0, f64_to_f32(frs1d));
else if(IS_INSN(CVT_D_W))
set_fp_reg(RRDR, 1, i32_to_f64(XRS1));
set_fp_reg(RRD, 1, i32_to_f64(XRS1));
else if(IS_INSN(CVT_D_L))
set_fp_reg(RRDR, 1, i64_to_f64(XRS1));
set_fp_reg(RRD, 1, i64_to_f64(XRS1));
else if(IS_INSN(CVT_D_S))
set_fp_reg(RRDR, 1, f32_to_f64(frs1s));
set_fp_reg(RRD, 1, f32_to_f64(frs1s));
else if(IS_INSN(CVTU_S_W))
set_fp_reg(RRDR, 0, ui32_to_f32(XRS1));
set_fp_reg(RRD, 0, ui32_to_f32(XRS1));
else if(IS_INSN(CVTU_S_L))
set_fp_reg(RRDR, 0, ui64_to_f32(XRS1));
set_fp_reg(RRD, 0, ui64_to_f32(XRS1));
else if(IS_INSN(CVTU_D_W))
set_fp_reg(RRDR, 1, ui32_to_f64(XRS1));
set_fp_reg(RRD, 1, ui32_to_f64(XRS1));
else if(IS_INSN(CVTU_D_L))
set_fp_reg(RRDR, 1, ui64_to_f64(XRS1));
set_fp_reg(RRD, 1, ui64_to_f64(XRS1));
else if(IS_INSN(ADD_S))
set_fp_reg(RRDR, 0, f32_add(frs1s, frs2s));
set_fp_reg(RRD, 0, f32_add(frs1s, frs2s));
else if(IS_INSN(ADD_D))
set_fp_reg(RRDR, 1, f64_add(frs1d, frs2d));
set_fp_reg(RRD, 1, f64_add(frs1d, frs2d));
else if(IS_INSN(SUB_S))
set_fp_reg(RRDR, 0, f32_sub(frs1s, frs2s));
set_fp_reg(RRD, 0, f32_sub(frs1s, frs2s));
else if(IS_INSN(SUB_D))
set_fp_reg(RRDR, 1, f64_sub(frs1d, frs2d));
set_fp_reg(RRD, 1, f64_sub(frs1d, frs2d));
else if(IS_INSN(MUL_S))
set_fp_reg(RRDR, 0, f32_mul(frs1s, frs2s));
set_fp_reg(RRD, 0, f32_mul(frs1s, frs2s));
else if(IS_INSN(MUL_D))
set_fp_reg(RRDR, 1, f64_mul(frs1d, frs2d));
set_fp_reg(RRD, 1, f64_mul(frs1d, frs2d));
else if(IS_INSN(MADD_S))
set_fp_reg(RRDR, 0, f32_mulAdd(frs1s, frs2s, frs3s));
set_fp_reg(RRD, 0, f32_mulAdd(frs1s, frs2s, frs3s));
else if(IS_INSN(MADD_D))
set_fp_reg(RRDR, 1, f64_mulAdd(frs1d, frs2d, frs3d));
set_fp_reg(RRD, 1, f64_mulAdd(frs1d, frs2d, frs3d));
else if(IS_INSN(MSUB_S))
set_fp_reg(RRDR, 0, f32_mulAdd(frs1s, frs2s, frs3s ^ (uint32_t)INT32_MIN));
set_fp_reg(RRD, 0, f32_mulAdd(frs1s, frs2s, frs3s ^ (uint32_t)INT32_MIN));
else if(IS_INSN(MSUB_D))
set_fp_reg(RRDR, 1, f64_mulAdd(frs1d, frs2d, frs3d ^ INT64_MIN));
set_fp_reg(RRD, 1, f64_mulAdd(frs1d, frs2d, frs3d ^ INT64_MIN));
else if(IS_INSN(NMADD_S))
set_fp_reg(RRDR, 0, f32_mulAdd(frs1s, frs2s, frs3s) ^ (uint32_t)INT32_MIN);
set_fp_reg(RRD, 0, f32_mulAdd(frs1s, frs2s, frs3s) ^ (uint32_t)INT32_MIN);
else if(IS_INSN(NMADD_D))
set_fp_reg(RRDR, 1, f64_mulAdd(frs1d, frs2d, frs3d) ^ INT64_MIN);
set_fp_reg(RRD, 1, f64_mulAdd(frs1d, frs2d, frs3d) ^ INT64_MIN);
else if(IS_INSN(NMSUB_S))
set_fp_reg(RRDR, 0, f32_mulAdd(frs1s, frs2s, frs3s ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN);
set_fp_reg(RRD, 0, f32_mulAdd(frs1s, frs2s, frs3s ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN);
else if(IS_INSN(NMSUB_D))
set_fp_reg(RRDR, 1, f64_mulAdd(frs1d, frs2d, frs3d ^ INT64_MIN) ^ INT64_MIN);
set_fp_reg(RRD, 1, f64_mulAdd(frs1d, frs2d, frs3d ^ INT64_MIN) ^ INT64_MIN);
else if(IS_INSN(DIV_S))
set_fp_reg(RRDR, 0, f32_div(frs1s, frs2s));
set_fp_reg(RRD, 0, f32_div(frs1s, frs2s));
else if(IS_INSN(DIV_D))
set_fp_reg(RRDR, 1, f64_div(frs1d, frs2d));
set_fp_reg(RRD, 1, f64_div(frs1d, frs2d));
else if(IS_INSN(SQRT_S))
set_fp_reg(RRDR, 0, f32_sqrt(frs1s));
set_fp_reg(RRD, 0, f32_sqrt(frs1s));
else if(IS_INSN(SQRT_D))
set_fp_reg(RRDR, 1, f64_sqrt(frs1d));
set_fp_reg(RRD, 1, f64_sqrt(frs1d));
else if(IS_INSN(CVT_W_S_RM))
{
softfloat_roundingMode = RM;

666
pk/riscv-opc.h
View File

@ -1,359 +1,357 @@
/* Automatically generated by parse-opcodes */
#define MATCH_MFF_D 0xd4006b00
#define MASK_MFF_D 0xfe0fffe0
#define MATCH_SGNINJ_D 0xd40060a0
#define MASK_SGNINJ_D 0xfe007fe0
#define MATCH_AMO_ADD 0xf4003000
#define MASK_AMO_ADD 0xfe007fe0
#define MATCH_CVT_D_L_RM 0xd4006580
#define MASK_CVT_D_L_RM 0xfff067e0
#define MATCH_REMUW 0xee0010e0
#define MASK_REMUW 0xfe007fe0
#define MATCH_MFF_D 0xd5ac0000
#define MASK_MFF_D 0xffff83e0
#define MATCH_SGNINJ_D 0xd5828000
#define MASK_SGNINJ_D 0xffff8000
#define MATCH_AMO_ADD 0xf4c00000
#define MASK_AMO_ADD 0xffff8000
#define MATCH_CVT_D_L_RM 0xd5c60000
#define MASK_CVT_D_L_RM 0xffcffc00
#define MATCH_REMUW 0xee438000
#define MASK_REMUW 0xffff8000
#define MATCH_NMADD_S 0xde000000
#define MASK_NMADD_S 0xfe007c00
#define MATCH_BLTU 0xe6006000
#define MASK_BLTU 0xfe007000
#define MATCH_C_EQ_S 0xd40002a0
#define MASK_C_EQ_S 0xfe007fe0
#define MATCH_SGNINJ_S 0xd40000a0
#define MASK_SGNINJ_S 0xfe007fe0
#define MATCH_DIV_D 0xd4006060
#define MASK_DIV_D 0xfe007fe0
#define MATCH_CVT_S_W 0xd40001c0
#define MASK_CVT_S_W 0xfff07fe0
#define MATCH_CVTU_S_W_RM 0xd40005e0
#define MASK_CVTU_S_W_RM 0xfff067e0
#define MATCH_NMADD_D 0xde006000
#define MASK_NMADD_D 0xfe007c00
#define MATCH_C_EQ_D 0xd40062a0
#define MASK_C_EQ_D 0xfe007fe0
#define MATCH_SLLIW 0xec007040
#define MASK_SLLIW 0xfe007fe0
#define MATCH_LB 0xf0000000
#define MASK_LB 0xfe007000
#define MATCH_CVT_L_S_RM 0xd4000500
#define MASK_CVT_L_S_RM 0xfff067e0
#define MATCH_CVTU_D_L 0xd40061a0
#define MASK_CVTU_D_L 0xfff07fe0
#define MATCH_LH 0xf0001000
#define MASK_LH 0xfe007000
#define MATCH_MSUB_S_RM 0xda000400
#define MASK_MSUB_S_RM 0xfe006400
#define MATCH_LW 0xf0002000
#define MASK_LW 0xfe007000
#define MASK_NMADD_S 0xfff00000
#define MATCH_BLTU 0xe7800000
#define MASK_BLTU 0xffc00000
#define MATCH_C_EQ_S 0xd40a8000
#define MASK_C_EQ_S 0xffff8000
#define MATCH_SGNINJ_S 0xd4028000
#define MASK_SGNINJ_S 0xffff8000
#define MATCH_DIV_D 0xd5818000
#define MASK_DIV_D 0xffff8000
#define MATCH_CVT_S_W 0xd4070000
#define MASK_CVT_S_W 0xfffffc00
#define MATCH_CVTU_S_W_RM 0xd4478000
#define MASK_CVTU_S_W_RM 0xffcffc00
#define MATCH_NMADD_D 0xdf800000
#define MASK_NMADD_D 0xfff00000
#define MATCH_C_EQ_D 0xd58a8000
#define MASK_C_EQ_D 0xffff8000
#define MATCH_SLLIW 0xedc10000
#define MASK_SLLIW 0xffff8000
#define MATCH_AMOW_MAX 0xf4828000
#define MASK_AMOW_MAX 0xffff8000
#define MATCH_CVT_L_S_RM 0xd4440000
#define MASK_CVT_L_S_RM 0xffcffc00
#define MATCH_CVTU_D_L 0xd5868000
#define MASK_CVTU_D_L 0xfffffc00
#define MATCH_LH 0xf0400000
#define MASK_LH 0xffc00000
#define MATCH_MSUB_S_RM 0xda400000
#define MASK_MSUB_S_RM 0xffc00000
#define MATCH_LW 0xf0800000
#define MASK_LW 0xffc00000
#define MATCH_ADD 0xea000000
#define MASK_ADD 0xfe007fe0
#define MATCH_CVT_W_D_RM 0xd4006540
#define MASK_CVT_W_D_RM 0xfff067e0
#define MATCH_AMOW_AND 0xf4002040
#define MASK_AMOW_AND 0xfe007fe0
#define MATCH_MFPCR 0xfc004000
#define MASK_MFPCR 0xfe0fffe0
#define MATCH_CVTU_D_W 0xd40061e0
#define MASK_CVTU_D_W 0xfff07fe0
#define MATCH_BNE 0xe6001000
#define MASK_BNE 0xfe007000
#define MATCH_MTPCR 0xfc005000
#define MASK_MTPCR 0xfe007fff
#define MASK_ADD 0xffff8000
#define MATCH_CVT_W_D_RM 0xd5c50000
#define MASK_CVT_W_D_RM 0xffcffc00
#define MATCH_AMOW_AND 0xf4810000
#define MASK_AMOW_AND 0xffff8000
#define MATCH_MFPCR 0xd6400000
#define MASK_MFPCR 0xffff83e0
#define MATCH_CVTU_D_W 0xd5878000
#define MASK_CVTU_D_W 0xfffffc00
#define MATCH_BNE 0xe6400000
#define MASK_BNE 0xffc00000
#define MATCH_MTPCR 0xd6408000
#define MASK_MTPCR 0xffff801f
#define MATCH_ADD_S 0xd4000000
#define MASK_ADD_S 0xfe007fe0
#define MATCH_BGEU 0xe6007000
#define MASK_BGEU 0xfe007000
#define MATCH_DI 0xfc001000
#define MASK_ADD_S 0xffff8000
#define MATCH_BGEU 0xe7c00000
#define MASK_BGEU 0xffc00000
#define MATCH_DI 0xd6008000
#define MASK_DI 0xffffffe0
#define MATCH_SLTIU 0xe8003000
#define MASK_SLTIU 0xfe007000
#define MATCH_MFFL_D 0xd4006b20
#define MASK_MFFL_D 0xfe0fffe0
#define MATCH_MADD_S_RM 0xd8000400
#define MASK_MADD_S_RM 0xfe006400
#define MATCH_BREAK 0xf6006000
#define MASK_BREAK 0xfffff000
#define MATCH_ADD_D 0xd4006000
#define MASK_ADD_D 0xfe007fe0
#define MATCH_MUL 0xea001000
#define MASK_MUL 0xfe007fe0
#define MATCH_AMOW_MIN 0xf4002080
#define MASK_AMOW_MIN 0xfe007fe0
#define MATCH_NOR 0xea0000e0
#define MASK_NOR 0xfe007fe0
#define MATCH_NMSUB_D 0xdc006000
#define MASK_NMSUB_D 0xfe007c00
#define MATCH_AMO_SWAP 0xf4003020
#define MASK_AMO_SWAP 0xfe007fe0
#define MATCH_CVTU_S_L_RM 0xd40005a0
#define MASK_CVTU_S_L_RM 0xfff067e0
#define MATCH_MADD_D_RM 0xd8006400
#define MASK_MADD_D_RM 0xfe006400
#define MATCH_SRLI 0xe8007080
#define MASK_SRLI 0xfe007fc0
#define MATCH_DIVUW 0xee0010a0
#define MASK_DIVUW 0xfe007fe0
#define MATCH_MFFH_D 0xd4006b40
#define MASK_MFFH_D 0xfe0fffe0
#define MATCH_SRLW 0xee007080
#define MASK_SRLW 0xfe007fe0
#define MATCH_SLTIU 0xe8c00000
#define MASK_SLTIU 0xffc00000
#define MATCH_MFFL_D 0xd5ac8000
#define MASK_MFFL_D 0xffff83e0
#define MATCH_MADD_S_RM 0xd8400000
#define MASK_MADD_S_RM 0xffc00000
#define MATCH_SGNMUL_D 0xd5838000
#define MASK_SGNMUL_D 0xffff8000
#define MATCH_ADD_D 0xd5800000
#define MASK_ADD_D 0xffff8000
#define MATCH_MUL 0xea400000
#define MASK_MUL 0xffff8000
#define MATCH_AMOW_MIN 0xf4820000
#define MASK_AMOW_MIN 0xffff8000
#define MATCH_NOR 0xea038000
#define MASK_NOR 0xffff8000
#define MATCH_NMSUB_D 0xdd800000
#define MASK_NMSUB_D 0xfff00000
#define MATCH_AMO_SWAP 0xf4c08000
#define MASK_AMO_SWAP 0xffff8000
#define MATCH_CVTU_S_L_RM 0xd4468000
#define MASK_CVTU_S_L_RM 0xffcffc00
#define MATCH_MADD_D_RM 0xd9c00000
#define MASK_MADD_D_RM 0xffc00000
#define MATCH_SRLI 0xe9c20000
#define MASK_SRLI 0xffff0000
#define MATCH_DIVUW 0xee428000
#define MASK_DIVUW 0xffff8000
#define MATCH_MFFH_D 0xd5ad0000
#define MASK_MFFH_D 0xffff83e0
#define MATCH_SRLW 0xefc20000
#define MASK_SRLW 0xffff8000
#define MATCH_NMSUB_S 0xdc000000
#define MASK_NMSUB_S 0xfe007c00
#define MATCH_MFCR 0xf6002000
#define MASK_MFCR 0xfe0fffe0
#define MATCH_C_LE_D 0xd40062e0
#define MASK_C_LE_D 0xfe007fe0
#define MATCH_DIV 0xea001080
#define MASK_DIV 0xfe007fe0
#define MATCH_MFF_S 0xd4000b00
#define MASK_MFF_S 0xfe0fffe0
#define MATCH_AMOW_OR 0xf4002060
#define MASK_AMOW_OR 0xfe007fe0
#define MATCH_EI 0xfc000000
#define MASK_NMSUB_S 0xfff00000
#define MATCH_MFCR 0xf6400000
#define MASK_MFCR 0xffff83e0
#define MATCH_C_LE_D 0xd58b8000
#define MASK_C_LE_D 0xffff8000
#define MATCH_DIV 0xea420000
#define MASK_DIV 0xffff8000
#define MATCH_MFF_S 0xd42c0000
#define MASK_MFF_S 0xffff83e0
#define MATCH_AMOW_OR 0xf4818000
#define MASK_AMOW_OR 0xffff8000
#define MATCH_EI 0xd6000000
#define MASK_EI 0xffffffe0
#define MATCH_SGNMUL_D 0xd40060e0
#define MASK_SGNMUL_D 0xfe007fe0
#define MATCH_SYNC 0xf6004000
#define MATCH_SYNC 0xf6800000
#define MASK_SYNC 0xffffffff
#define MATCH_MTF_S 0xd4000b80
#define MASK_MTF_S 0xfff07fe0
#define MATCH_CVTU_W_D_RM 0xd4006560
#define MASK_CVTU_W_D_RM 0xfff067e0
#define MATCH_S_S 0xd2002000
#define MASK_S_S 0xfe007000
#define MATCH_MTCR 0xf6003000
#define MASK_MTCR 0xfe007fff
#define MATCH_MTF_S 0xd42e0000
#define MASK_MTF_S 0xfffffc00
#define MATCH_CVTU_W_D_RM 0xd5c58000
#define MASK_CVTU_W_D_RM 0xffcffc00
#define MATCH_S_S 0xd2800000
#define MASK_S_S 0xffc00000
#define MATCH_MTCR 0xf6408000
#define MASK_MTCR 0xffff801f
#define MATCH_MSUB_S 0xda000000
#define MASK_MSUB_S 0xfe007c00
#define MASK_MSUB_S 0xfff00000
#define MATCH_ADDW 0xee000000
#define MASK_ADDW 0xfe007fe0
#define MATCH_SLTU 0xea000060
#define MASK_SLTU 0xfe007fe0
#define MATCH_XOR 0xea0000c0
#define MASK_XOR 0xfe007fe0
#define MATCH_SUB 0xea000020
#define MASK_SUB 0xfe007fe0
#define MATCH_ERET 0xfc002000
#define MASK_ADDW 0xffff8000
#define MATCH_SLTU 0xea018000
#define MASK_SLTU 0xffff8000
#define MATCH_XOR 0xea030000
#define MASK_XOR 0xffff8000
#define MATCH_SUB 0xea008000
#define MASK_SUB 0xffff8000
#define MATCH_ERET 0xd6800000
#define MASK_ERET 0xffffffff
#define MATCH_SQRT_D_RM 0xd4006480
#define MASK_SQRT_D_RM 0xfff067e0
#define MATCH_BLT 0xe6004000
#define MASK_BLT 0xfe007000
#define MATCH_SGNINJN_D 0xd40060c0
#define MASK_SGNINJN_D 0xfe007fe0
#define MATCH_REM 0xea0010c0
#define MASK_REM 0xfe007fe0
#define MATCH_SRLIW 0xec007080
#define MASK_SRLIW 0xfe007fe0
#define MATCH_SQRT_D_RM 0xd5c20000
#define MASK_SQRT_D_RM 0xffcffc00
#define MATCH_BLT 0xe7000000
#define MASK_BLT 0xffc00000
#define MATCH_SGNINJN_D 0xd5830000
#define MASK_SGNINJN_D 0xffff8000
#define MATCH_REM 0xea430000
#define MASK_REM 0xffff8000
#define MATCH_SRLIW 0xedc20000
#define MASK_SRLIW 0xffff8000
#define MATCH_LUI 0xe2000000
#define MASK_LUI 0xfe000000
#define MATCH_CVTU_D_L_RM 0xd40065a0
#define MASK_CVTU_D_L_RM 0xfff067e0
#define MATCH_CVTU_D_L_RM 0xd5c68000
#define MASK_CVTU_D_L_RM 0xffcffc00
#define MATCH_ADDI 0xe8000000
#define MASK_ADDI 0xfe007000
#define MATCH_ADD_D_RM 0xd4006400
#define MASK_ADD_D_RM 0xfe0067e0
#define MATCH_MULH 0xea001040
#define MASK_MULH 0xfe007fe0
#define MATCH_MULHUW 0xee001060
#define MASK_MULHUW 0xfe007fe0
#define MATCH_SGNINJN_S 0xd40000c0
#define MASK_SGNINJN_S 0xfe007fe0
#define MATCH_SRAI 0xe80070c0
#define MASK_SRAI 0xfe007fc0
#define MATCH_SRAW 0xee0070c0
#define MASK_SRAW 0xfe007fe0
#define MATCH_LD 0xf0003000
#define MASK_LD 0xfe007000
#define MATCH_ORI 0xe8005000
#define MASK_ORI 0xfe007000
#define MATCH_CVT_L_D_RM 0xd4006500
#define MASK_CVT_L_D_RM 0xfff067e0
#define MATCH_AMOW_MAX 0xf40020a0
#define MASK_AMOW_MAX 0xfe007fe0
#define MASK_ADDI 0xffc00000
#define MATCH_ADD_D_RM 0xd5c00000
#define MASK_ADD_D_RM 0xffcf8000
#define MATCH_MULH 0xea410000
#define MASK_MULH 0xffff8000
#define MATCH_MULHUW 0xee418000
#define MASK_MULHUW 0xffff8000
#define MATCH_SGNINJN_S 0xd4030000
#define MASK_SGNINJN_S 0xffff8000
#define MATCH_SRAI 0xe9c30000
#define MASK_SRAI 0xffff0000
#define MATCH_SRAW 0xefc30000
#define MASK_SRAW 0xffff8000
#define MATCH_LD 0xf0c00000
#define MASK_LD 0xffc00000
#define MATCH_ORI 0xe9400000
#define MASK_ORI 0xffc00000
#define MATCH_CVT_L_D_RM 0xd5c40000
#define MASK_CVT_L_D_RM 0xffcffc00
#define MATCH_LB 0xf0000000
#define MASK_LB 0xffc00000
#define MATCH_ADDIW 0xec000000
#define MASK_ADDIW 0xfe007000
#define MATCH_MULW 0xee001000
#define MASK_MULW 0xfe007fe0
#define MATCH_MTFLH_D 0xd4006f80
#define MASK_MTFLH_D 0xfe007fe0
#define MATCH_MUL_S_RM 0xd4000440
#define MASK_MUL_S_RM 0xfe0067e0
#define MATCH_SRA 0xea0070c0
#define MASK_SRA 0xfe007fe0
#define MATCH_BGE 0xe6005000
#define MASK_BGE 0xfe007000
#define MATCH_SRAIW 0xec0070c0
#define MASK_SRAIW 0xfe007fe0
#define MATCH_SRL 0xea007080
#define MASK_SRL 0xfe007fe0
#define MATCH_CVTU_L_S_RM 0xd4000520
#define MASK_CVTU_L_S_RM 0xfff067e0
#define MATCH_NMSUB_D_RM 0xdc006400
#define MASK_NMSUB_D_RM 0xfe006400
#define MATCH_NMSUB_S_RM 0xdc000400
#define MASK_NMSUB_S_RM 0xfe006400
#define MATCH_OR 0xea0000a0
#define MASK_OR 0xfe007fe0
#define MATCH_CVT_S_W_RM 0xd40005c0
#define MASK_CVT_S_W_RM 0xfff067e0
#define MATCH_SUBW 0xee000020
#define MASK_SUBW 0xfe007fe0
#define MATCH_JALR_C 0xf6000000
#define MASK_JALR_C 0xfff07fe0
#define MATCH_CVTU_S_W 0xd40001e0
#define MASK_CVTU_S_W 0xfff07fe0
#define MATCH_AMOW_MINU 0xf40020c0
#define MASK_AMOW_MINU 0xfe007fe0
#define MATCH_JALR_J 0xf6000040
#define MASK_JALR_J 0xfff07fe0
#define MATCH_S_D 0xd2003000
#define MASK_S_D 0xfe007000
#define MATCH_AMO_OR 0xf4003060
#define MASK_AMO_OR 0xfe007fe0
#define MATCH_XORI 0xe8006000
#define MASK_XORI 0xfe007000
#define MATCH_JALR_R 0xf6000020
#define MASK_JALR_R 0xfff07fe0
#define MATCH_NMADD_S_RM 0xde000400
#define MASK_NMADD_S_RM 0xfe006400
#define MATCH_CVTU_S_L 0xd40001a0
#define MASK_CVTU_S_L 0xfff07fe0
#define MATCH_AMO_MAX 0xf40030a0
#define MASK_AMO_MAX 0xfe007fe0
#define MATCH_AMO_MIN 0xf4003080
#define MASK_AMO_MIN 0xfe007fe0
#define MATCH_ANDI 0xe8004000
#define MASK_ANDI 0xfe007000
#define MATCH_SQRT_S_RM 0xd4000480
#define MASK_SQRT_S_RM 0xfff067e0
#define MATCH_CVTU_L_D_RM 0xd4006520
#define MASK_CVTU_L_D_RM 0xfff067e0
#define MASK_ADDIW 0xffc00000
#define MATCH_MULW 0xee400000
#define MASK_MULW 0xffff8000
#define MATCH_MTFLH_D 0xd5be0000
#define MASK_MTFLH_D 0xffff8000
#define MATCH_MUL_S_RM 0xd4410000
#define MASK_MUL_S_RM 0xffcf8000
#define MATCH_SRA 0xebc30000
#define MASK_SRA 0xffff8000
#define MATCH_BGE 0xe7400000
#define MASK_BGE 0xffc00000
#define MATCH_SRAIW 0xedc30000
#define MASK_SRAIW 0xffff8000
#define MATCH_SRL 0xebc20000
#define MASK_SRL 0xffff8000
#define MATCH_CVTU_L_S_RM 0xd4448000
#define MASK_CVTU_L_S_RM 0xffcffc00
#define MATCH_NMSUB_D_RM 0xddc00000
#define MASK_NMSUB_D_RM 0xffc00000
#define MATCH_NMSUB_S_RM 0xdc400000
#define MASK_NMSUB_S_RM 0xffc00000
#define MATCH_OR 0xea028000
#define MASK_OR 0xffff8000
#define MATCH_CVT_S_W_RM 0xd4470000
#define MASK_CVT_S_W_RM 0xffcffc00
#define MATCH_SUBW 0xee008000
#define MASK_SUBW 0xffff8000
#define MATCH_JALR_C 0xe4000000
#define MASK_JALR_C 0xffc00000
#define MATCH_CVTU_S_W 0xd4078000
#define MASK_CVTU_S_W 0xfffffc00
#define MATCH_AMOW_MINU 0xf4830000
#define MASK_AMOW_MINU 0xffff8000
#define MATCH_JALR_J 0xe4800000
#define MASK_JALR_J 0xffc00000
#define MATCH_S_D 0xd2c00000
#define MASK_S_D 0xffc00000
#define MATCH_AMO_OR 0xf4c18000
#define MASK_AMO_OR 0xffff8000
#define MATCH_XORI 0xe9800000
#define MASK_XORI 0xffc00000
#define MATCH_JALR_R 0xe4400000
#define MASK_JALR_R 0xffc00000
#define MATCH_NMADD_S_RM 0xde400000
#define MASK_NMADD_S_RM 0xffc00000
#define MATCH_CVTU_S_L 0xd4068000
#define MASK_CVTU_S_L 0xfffffc00
#define MATCH_AMO_MAX 0xf4c28000
#define MASK_AMO_MAX 0xffff8000
#define MATCH_AMO_MIN 0xf4c20000
#define MASK_AMO_MIN 0xffff8000
#define MATCH_ANDI 0xe9000000
#define MASK_ANDI 0xffc00000
#define MATCH_SQRT_S_RM 0xd4420000
#define MASK_SQRT_S_RM 0xffcffc00
#define MATCH_CVTU_L_D_RM 0xd5c48000
#define MASK_CVTU_L_D_RM 0xffcffc00
#define MATCH_JAL 0xc2000000
#define MASK_JAL 0xfe000000
#define MATCH_LWU 0xf0006000
#define MASK_LWU 0xfe007000
#define MATCH_CVT_S_D_RM 0xd4000660
#define MASK_CVT_S_D_RM 0xfff067e0
#define MATCH_AMO_MINU 0xf40030c0
#define MASK_AMO_MINU 0xfe007fe0
#define MATCH_SUB_S_RM 0xd4000420
#define MASK_SUB_S_RM 0xfe0067e0
#define MATCH_CVT_S_L 0xd4000180
#define MASK_CVT_S_L 0xfff07fe0
#define MATCH_DIV_S_RM 0xd4000460
#define MASK_DIV_S_RM 0xfe0067e0
#define MATCH_MUL_D_RM 0xd4006440
#define MASK_MUL_D_RM 0xfe0067e0
#define MATCH_SUB_S 0xd4000020
#define MASK_SUB_S 0xfe007fe0
#define MATCH_NMADD_D_RM 0xde006400
#define MASK_NMADD_D_RM 0xfe006400
#define MATCH_SLT 0xea000040
#define MASK_SLT 0xfe007fe0
#define MATCH_SLLW 0xee007040
#define MASK_SLLW 0xfe007fe0
#define MATCH_LWU 0xf1800000
#define MASK_LWU 0xffc00000
#define MATCH_CVT_S_D_RM 0xd4498000
#define MASK_CVT_S_D_RM 0xffcffc00
#define MATCH_AMO_MINU 0xf4c30000
#define MASK_AMO_MINU 0xffff8000
#define MATCH_SUB_S_RM 0xd4408000
#define MASK_SUB_S_RM 0xffcf8000
#define MATCH_CVT_S_L 0xd4060000
#define MASK_CVT_S_L 0xfffffc00
#define MATCH_DIV_S_RM 0xd4418000
#define MASK_DIV_S_RM 0xffcf8000
#define MATCH_MUL_D_RM 0xd5c10000
#define MASK_MUL_D_RM 0xffcf8000
#define MATCH_SUB_S 0xd4008000
#define MASK_SUB_S 0xffff8000
#define MATCH_NMADD_D_RM 0xdfc00000
#define MASK_NMADD_D_RM 0xffc00000
#define MATCH_SLT 0xea010000
#define MASK_SLT 0xffff8000
#define MATCH_SLLW 0xefc10000
#define MASK_SLLW 0xffff8000
#define MATCH_J 0xc0000000
#define MASK_J 0xfe000000
#define MATCH_SLTI 0xe8002000
#define MASK_SLTI 0xfe007000
#define MATCH_REMU 0xea0010e0
#define MASK_REMU 0xfe007fe0
#define MATCH_REMW 0xee0010c0
#define MASK_REMW 0xfe007fe0
#define MATCH_SLL 0xea007040
#define MASK_SLL 0xfe007fe0
#define MATCH_SLLI 0xe8007040
#define MASK_SLLI 0xfe007fc0
#define MATCH_SUB_D 0xd4006020
#define MASK_SUB_D 0xfe007fe0
#define MATCH_CVT_S_L_RM 0xd4000580
#define MASK_CVT_S_L_RM 0xfff067e0
#define MATCH_SLTI 0xe8800000
#define MASK_SLTI 0xffc00000
#define MATCH_REMU 0xea438000
#define MASK_REMU 0xffff8000
#define MATCH_REMW 0xee430000
#define MASK_REMW 0xffff8000
#define MATCH_SLL 0xebc10000
#define MASK_SLL 0xffff8000
#define MATCH_SLLI 0xe9c10000
#define MASK_SLLI 0xffff0000
#define MATCH_SUB_D 0xd5808000
#define MASK_SUB_D 0xffff8000
#define MATCH_CVT_S_L_RM 0xd4460000
#define MASK_CVT_S_L_RM 0xffcffc00
#define MATCH_BEQ 0xe6000000
#define MASK_BEQ 0xfe007000
#define MATCH_AND 0xea000080
#define MASK_AND 0xfe007fe0
#define MATCH_LBU 0xf0004000
#define MASK_LBU 0xfe007000
#define MATCH_SQRT_S 0xd4000080
#define MASK_SQRT_S 0xfff07fe0
#define MATCH_SYSCALL 0xf6005000
#define MASK_SYSCALL 0xfffff000
#define MATCH_C_LT_S 0xd40002c0
#define MASK_C_LT_S 0xfe007fe0
#define MATCH_MTF_D 0xd4006b80
#define MASK_MTF_D 0xfff07fe0
#define MATCH_SQRT_D 0xd4006080
#define MASK_SQRT_D 0xfff07fe0
#define MATCH_ADD_S_RM 0xd4000400
#define MASK_ADD_S_RM 0xfe0067e0
#define MATCH_AMOW_ADD 0xf4002000
#define MASK_AMOW_ADD 0xfe007fe0
#define MATCH_MULHW 0xee001040
#define MASK_MULHW 0xfe007fe0
#define MASK_BEQ 0xffc00000
#define MATCH_AND 0xea020000
#define MASK_AND 0xffff8000
#define MATCH_LBU 0xf1000000
#define MASK_LBU 0xffc00000
#define MATCH_SQRT_S 0xd4020000
#define MASK_SQRT_S 0xfffffc00
#define MATCH_SYSCALL 0xf6c00000
#define MASK_SYSCALL 0xffc003ff
#define MATCH_C_LT_S 0xd40b0000
#define MASK_C_LT_S 0xffff8000
#define MATCH_MTF_D 0xd5ae0000
#define MASK_MTF_D 0xfffffc00
#define MATCH_SQRT_D 0xd5820000
#define MASK_SQRT_D 0xfffffc00
#define MATCH_ADD_S_RM 0xd4400000
#define MASK_ADD_S_RM 0xffcf8000
#define MATCH_AMOW_ADD 0xf4800000
#define MASK_AMOW_ADD 0xffff8000
#define MATCH_MULHW 0xee410000
#define MASK_MULHW 0xffff8000
#define MATCH_MADD_S 0xd8000000
#define MASK_MADD_S 0xfe007c00
#define MATCH_MULHU 0xea001060
#define MASK_MULHU 0xfe007fe0
#define MATCH_AMO_AND 0xf4003040
#define MASK_AMO_AND 0xfe007fe0
#define MATCH_MSUB_D 0xda006000
#define MASK_MSUB_D 0xfe007c00
#define MATCH_SGNMUL_S 0xd40000e0
#define MASK_SGNMUL_S 0xfe007fe0
#define MATCH_RDNPC 0xf6001000
#define MASK_MADD_S 0xfff00000
#define MATCH_MULHU 0xea418000
#define MASK_MULHU 0xffff8000
#define MATCH_AMO_AND 0xf4c10000
#define MASK_AMO_AND 0xffff8000
#define MATCH_MSUB_D 0xdb800000
#define MASK_MSUB_D 0xfff00000
#define MATCH_SGNMUL_S 0xd4038000
#define MASK_SGNMUL_S 0xffff8000
#define MATCH_RDNPC 0xf6000000
#define MASK_RDNPC 0xffffffe0
#define MATCH_DIV_D_RM 0xd4006460
#define MASK_DIV_D_RM 0xfe0067e0
#define MATCH_MADD_D 0xd8006000
#define MASK_MADD_D 0xfe007c00
#define MATCH_SYNCI 0xf0007000
#define MASK_SYNCI 0xfff07000
#define MATCH_DIV_S 0xd4000060
#define MASK_DIV_S 0xfe007fe0
#define MATCH_DIV_D_RM 0xd5c18000
#define MASK_DIV_D_RM 0xffcf8000
#define MATCH_MADD_D 0xd9800000
#define MASK_MADD_D 0xfff00000
#define MATCH_SYNCI 0xf1c00000
#define MASK_SYNCI 0xffc0001f
#define MATCH_DIV_S 0xd4018000
#define MASK_DIV_S 0xffff8000
#define MATCH_UNIMP 0x0
#define MASK_UNIMP 0xffffffff
#define MATCH_CVT_S_D 0xd4000260
#define MASK_CVT_S_D 0xfff07fe0
#define MATCH_C_LE_S 0xd40002e0
#define MASK_C_LE_S 0xfe007fe0
#define MATCH_MUL_S 0xd4000040
#define MASK_MUL_S 0xfe007fe0
#define MATCH_CVT_W_S_RM 0xd4000540
#define MASK_CVT_W_S_RM 0xfff067e0
#define MATCH_CVT_D_S 0xd4006200
#define MASK_CVT_D_S 0xfff07fe0
#define MATCH_CVT_D_W 0xd40061c0
#define MASK_CVT_D_W 0xfff07fe0
#define MATCH_L_S 0xd0002000
#define MASK_L_S 0xfe007000
#define MATCH_CVT_D_L 0xd4006180
#define MASK_CVT_D_L 0xfff07fe0
#define MATCH_DIVW 0xee001080
#define MASK_DIVW 0xfe007fe0
#define MATCH_L_D 0xd0003000
#define MASK_L_D 0xfe007000
#define MATCH_DIVU 0xea0010a0
#define MASK_DIVU 0xfe007fe0
#define MATCH_MUL_D 0xd4006040
#define MASK_MUL_D 0xfe007fe0
#define MATCH_MSUB_D_RM 0xda006400
#define MASK_MSUB_D_RM 0xfe006400
#define MATCH_SW 0xf2002000
#define MASK_SW 0xfe007000
#define MATCH_AMOW_SWAP 0xf4002020
#define MASK_AMOW_SWAP 0xfe007fe0
#define MATCH_LHU 0xf0005000
#define MASK_LHU 0xfe007000
#define MATCH_SH 0xf2001000
#define MASK_SH 0xfe007000
#define MATCH_AMO_MAXU 0xf40030e0
#define MASK_AMO_MAXU 0xfe007fe0
#define MATCH_AMOW_MAXU 0xf40020e0
#define MASK_AMOW_MAXU 0xfe007fe0
#define MATCH_CVT_S_D 0xd4098000
#define MASK_CVT_S_D 0xfffffc00
#define MATCH_C_LE_S 0xd40b8000
#define MASK_C_LE_S 0xffff8000
#define MATCH_MUL_S 0xd4010000
#define MASK_MUL_S 0xffff8000
#define MATCH_CVT_W_S_RM 0xd4450000
#define MASK_CVT_W_S_RM 0xffcffc00
#define MATCH_CVT_D_S 0xd5880000
#define MASK_CVT_D_S 0xfffffc00
#define MATCH_CVT_D_W 0xd5870000
#define MASK_CVT_D_W 0xfffffc00
#define MATCH_L_S 0xd0800000
#define MASK_L_S 0xffc00000
#define MATCH_CVT_D_L 0xd5860000
#define MASK_CVT_D_L 0xfffffc00
#define MATCH_DIVW 0xee420000
#define MASK_DIVW 0xffff8000
#define MATCH_L_D 0xd0c00000
#define MASK_L_D 0xffc00000
#define MATCH_DIVU 0xea428000
#define MASK_DIVU 0xffff8000
#define MATCH_MUL_D 0xd5810000
#define MASK_MUL_D 0xffff8000
#define MATCH_MSUB_D_RM 0xdbc00000
#define MASK_MSUB_D_RM 0xffc00000
#define MATCH_SW 0xf2800000
#define MASK_SW 0xffc00000
#define MATCH_AMOW_SWAP 0xf4808000
#define MASK_AMOW_SWAP 0xffff8000
#define MATCH_LHU 0xf1400000
#define MASK_LHU 0xffc00000
#define MATCH_SH 0xf2400000
#define MASK_SH 0xffc00000
#define MATCH_AMO_MAXU 0xf4c38000
#define MASK_AMO_MAXU 0xffff8000
#define MATCH_AMOW_MAXU 0xf4838000
#define MASK_AMOW_MAXU 0xffff8000
#define MATCH_SB 0xf2000000
#define MASK_SB 0xfe007000
#define MATCH_C_LT_D 0xd40062c0
#define MASK_C_LT_D 0xfe007fe0
#define MATCH_CVTU_W_S_RM 0xd4000560
#define MASK_CVTU_W_S_RM 0xfff067e0
#define MATCH_SUB_D_RM 0xd4006420
#define MASK_SUB_D_RM 0xfe0067e0
#define MATCH_SD 0xf2003000
#define MASK_SD 0xfe007000
#define MASK_SB 0xffc00000
#define MATCH_C_LT_D 0xd58b0000
#define MASK_C_LT_D 0xffff8000
#define MATCH_CVTU_W_S_RM 0xd4458000
#define MASK_CVTU_W_S_RM 0xffcffc00
#define MATCH_SUB_D_RM 0xd5c08000
#define MASK_SUB_D_RM 0xffcf8000
#define MATCH_SD 0xf2c00000
#define MASK_SD 0xffc00000

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