Add __riscv_flush_icache

For BBL's purposes a local i-cache flush should be sufficient.
9 years ago · 15ff218ec0
2 changed files with 4 additions and 0 deletions
--- a/machine/flush_icache.c
+++ b/machine/flush_icache.c
@ -0,0 +1,3 @@
+void __riscv_flush_icache(void) {
+  __asm__ volatile ("fence.i");
+}
--- a/machine/machine.mk.in
+++ b/machine/machine.mk.in
@ -28,6 +28,7 @@ machine_c_srcs = \
  uart.c \
  finisher.c \
  misaligned_ldst.c \
+  flush_icache.c \

 machine_asm_srcs = \
  mentry.S \