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riscv-isa-sim
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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/hwacha
Andrew Waterman 416c8be88c
Support building from within root directory 		12 years ago
..
insns Support 2/4/6/8-byte instructions 12 years ago
insns_ut Add ut_fclass_s/d hwacha (unused until encoding sync) 12 years ago
README revamp hwacha; now runs in physical mode 13 years ago
cvt16.cc Implement "half-baked" half-precision instruction subset for Hwacha 13 years ago
cvt16.h Implement "half-baked" half-precision instruction subset for Hwacha 13 years ago
decode_hwacha.h zero-extend 32b instructions for vxcptaux 12 years ago
decode_hwacha_ut.h Move half precision instructions, add vfmsv, vfmvv 12 years ago
encodings_hwacha.h add hwacha vfmsv instructions 12 years ago
hwacha.ac revamp hwacha; now runs in physical mode 13 years ago
hwacha.cc zero-extend 32b instructions for vxcptaux 12 years ago
hwacha.h Fix linking on Darwin 12 years ago
hwacha.mk.in Support building from within root directory 12 years ago
hwacha_disasm.cc add hwacha vfmsv instructions 12 years ago
hwacha_xcpt.h add hwacha exception support 13 years ago
insn_template_hwacha.cc Use precompiled headers to speed up compilation 12 years ago
insn_template_hwacha.h Use precompiled headers to speed up compilation 12 years ago
insn_template_hwacha_ut.cc Use precompiled headers to speed up compilation 12 years ago
insn_template_hwacha_ut.h Avoid use of __int128_t 12 years ago
opcodes_hwacha.h add hwacha vfmsv instructions 12 years ago
opcodes_hwacha_ut.h Sync encoding in opcodes 12 years ago

README 

This directory contains work in progress on Hwacha, a data-parallel
accelerator.