Spike, a RISC-V ISA Simulator

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Tree: cec752d091

arrv-sc-arrv-sc/snippy-tests

confprec

cs250

cycleh

debug_rom

debug_rom_fence

device_flags

dtm_reset_error

dts_parsing

dynamic

eos18-bringup

factor-out-macros

fetch

fix-2296

fix-bf16

force-rtti

fp-encoding

heterogeneous_mc

hwachav4

increase-stack-size

itrigger-etrigger-cleanup

load_reservation_set_size

log-commits-faster

master

mmio-hack

mvp

no_progbuf

no_progbuf2

nolibfdt

optimized-chunk-size

p-ext-0.5.2

plctlab-plct-zce-fix2

plic-clint-endian

plic_uart_v1

priv-1.10

private-l1-caches

pte-info-and-delegation

remove-tests

rivosinc-etrigger_fix_exception_match

rva-profile-support

sanitize

simplify-misaligned

sodor

sparse-mem

speed2

speedup-hacks

static-link

test

tmp

trigger_priority

tweak_debug_rom

whole-archive

zvmm

dummy-tag-for-ci-storage

v1.0.0

v1.1.0

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riscv-isa-sim/spike

History

Andrew Waterman b06c8e9f26 Implement timer faithfully rdcycle/rdinstret now have single-instruction granularity. Questionable behavior when timer interrupts occurred around the same time as the compare register is written should be fixed.		12 years ago
..
disasm.cc	added support for register convention names in debug mode	12 years ago
extensions.cc	Factor out the dummy RoCC accelerator	12 years ago
riscv-dis.cc	Factor out the dummy RoCC accelerator	12 years ago
spike.ac	Enable runtime loading of dynamic library with --extlib	12 years ago
spike.cc	Factor out the dummy RoCC accelerator	12 years ago
spike.mk.in	Implement timer faithfully	12 years ago
termios-xspike.cc	Eliminate hwacha <-> riscv circular dependence	12 years ago
xspike.cc	Eliminate hwacha <-> riscv circular dependence	12 years ago