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113 lines
3.0 KiB
113 lines
3.0 KiB
// See LICENSE for license details.
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#ifndef _RISCV_PCR_H
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#define _RISCV_PCR_H
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#define SR_S 0x00000001
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#define SR_PS 0x00000002
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#define SR_EI 0x00000004
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#define SR_PEI 0x00000008
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#define SR_EF 0x00000010
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#define SR_U64 0x00000020
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#define SR_S64 0x00000040
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#define SR_VM 0x00000080
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#define SR_EV 0x00000100
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#define SR_IM 0x00FF0000
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#define SR_IP 0xFF000000
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#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EV|SR_IM|SR_IP)
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#define SR_IM_SHIFT 16
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#define SR_IP_SHIFT 24
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#define PCR_SUP0 0
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#define PCR_SUP1 1
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#define PCR_EPC 2
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#define PCR_BADVADDR 3
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#define PCR_PTBR 4
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#define PCR_ASID 5
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#define PCR_COUNT 6
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#define PCR_COMPARE 7
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#define PCR_EVEC 8
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#define PCR_CAUSE 9
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#define PCR_SR 10
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#define PCR_HARTID 11
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#define PCR_IMPL 12
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#define PCR_FATC 13
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#define PCR_SEND_IPI 14
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#define PCR_CLR_IPI 15
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#define PCR_VECBANK 18
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#define PCR_VECCFG 19
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#define PCR_RESET 29
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#define PCR_TOHOST 30
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#define PCR_FROMHOST 31
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#define IRQ_COP 2
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#define IRQ_IPI 5
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#define IRQ_HOST 6
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#define IRQ_TIMER 7
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#define IMPL_SPIKE 1
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#define IMPL_ROCKET 2
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#define CAUSE_MISALIGNED_FETCH 0
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#define CAUSE_FAULT_FETCH 1
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#define CAUSE_ILLEGAL_INSTRUCTION 2
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#define CAUSE_PRIVILEGED_INSTRUCTION 3
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#define CAUSE_FP_DISABLED 4
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#define CAUSE_SYSCALL 6
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#define CAUSE_BREAKPOINT 7
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#define CAUSE_MISALIGNED_LOAD 8
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#define CAUSE_MISALIGNED_STORE 9
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#define CAUSE_FAULT_LOAD 10
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#define CAUSE_FAULT_STORE 11
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// page table entry (PTE) fields
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#define PTE_V 0x001 // Entry is a page Table descriptor
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#define PTE_T 0x002 // Entry is a page Table, not a terminal node
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#define PTE_G 0x004 // Global
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#define PTE_UR 0x008 // User Write permission
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#define PTE_UW 0x010 // User Read permission
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#define PTE_UX 0x020 // User eXecute permission
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#define PTE_SR 0x040 // Supervisor Read permission
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#define PTE_SW 0x080 // Supervisor Write permission
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#define PTE_SX 0x100 // Supervisor eXecute permission
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#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX)
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#ifdef __riscv
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#ifdef __riscv64
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# define RISCV_PGLEVELS 3
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# define RISCV_PGSHIFT 13
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#else
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# define RISCV_PGLEVELS 2
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# define RISCV_PGSHIFT 12
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#endif
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#define RISCV_PGLEVEL_BITS 10
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#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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#ifndef __ASSEMBLER__
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#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \
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asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \
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__tmp2; })
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#define mfpcr(reg) ({ long __tmp; \
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asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \
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__tmp; })
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#define setpcr(reg,val) ({ long __tmp; \
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asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
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__tmp; })
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#define clearpcr(reg,val) ({ long __tmp; \
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asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \
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__tmp; })
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#define rdcycle() ({ unsigned long __tmp; \
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asm volatile ("rdcycle %0" : "=r"(__tmp)); \
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__tmp; })
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#endif
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#endif
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#endif
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