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72 lines
2.4 KiB
72 lines
2.4 KiB
hwacha_disassembler::hwacha_disassembler()
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{
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#define DEFINE_RS1(code) DISASM_INSN(#code, code, 0, xrs1_reg)
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#define DEFINE_RS1_RS2(code) DISASM_INSN(#code, code, 0, xrs1_reg, xrs2_reg)
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#define DEFINE_VEC_XMEM(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg)
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#define DEFINE_VEC_XMEMST(code) DISASM_INSN(#code, code, 0, vxrd_reg, xrs1_reg, xrs2_reg)
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#define DEFINE_VEC_FMEM(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg)
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#define DEFINE_VEC_FMEMST(code) DISASM_INSN(#code, code, 0, vfrd_reg, xrs1_reg, xrs2_reg)
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DEFINE_RS1(vxcptsave);
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DEFINE_RS1(vxcptrestore);
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DEFINE_NOARG(vxcptkill);
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DEFINE_RS1(vxcptevac);
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DEFINE_NOARG(vxcpthold);
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DEFINE_RS1_RS2(venqcmd);
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DEFINE_RS1_RS2(venqimm1);
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DEFINE_RS1_RS2(venqimm2);
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DEFINE_RS1_RS2(venqcnt);
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DEFINE_VEC_XMEM(vld);
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DEFINE_VEC_XMEM(vlw);
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DEFINE_VEC_XMEM(vlwu);
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DEFINE_VEC_XMEM(vlh);
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DEFINE_VEC_XMEM(vlhu);
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DEFINE_VEC_XMEM(vlb);
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DEFINE_VEC_XMEM(vlbu);
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DEFINE_VEC_FMEM(vfld);
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DEFINE_VEC_FMEM(vflw);
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DEFINE_VEC_XMEMST(vlstd);
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DEFINE_VEC_XMEMST(vlstw);
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DEFINE_VEC_XMEMST(vlstwu);
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DEFINE_VEC_XMEMST(vlsth);
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DEFINE_VEC_XMEMST(vlsthu);
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DEFINE_VEC_XMEMST(vlstb);
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DEFINE_VEC_XMEMST(vlstbu);
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DEFINE_VEC_FMEMST(vflstd);
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DEFINE_VEC_FMEMST(vflstw);
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DEFINE_VEC_XMEM(vsd);
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DEFINE_VEC_XMEM(vsw);
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DEFINE_VEC_XMEM(vsh);
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DEFINE_VEC_XMEM(vsb);
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DEFINE_VEC_FMEM(vfsd);
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DEFINE_VEC_FMEM(vfsw);
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DEFINE_VEC_XMEMST(vsstd);
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DEFINE_VEC_XMEMST(vsstw);
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DEFINE_VEC_XMEMST(vssth);
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DEFINE_VEC_XMEMST(vsstb);
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DEFINE_VEC_FMEMST(vfsstd);
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DEFINE_VEC_FMEMST(vfsstw);
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DISASM_INSN("vmvv", vmvv, 0, vxrd_reg, vxrs1_reg);
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DISASM_INSN("vmsv", vmsv, 0, vxrd_reg, xrs1_reg);
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DISASM_INSN("vmst", vmst, 0, vxrd_reg, xrs1_reg, xrs2_reg);
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DISASM_INSN("vmts", vmts, 0, xrd_reg, vxrs1_reg, xrs2_reg);
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DISASM_INSN("vfmvv", vfmvv, 0, vfrd_reg, vfrs1_reg);
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DISASM_INSN("vfmsv", vfmsv, 0, vfrd_reg, frs1_reg);
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DISASM_INSN("vfmst", vfmst, 0, vfrd_reg, frs1_reg, frs2_reg);
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DISASM_INSN("vfmts", vfmts, 0, frd_reg, vfrs1_reg, frs2_reg);
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DEFINE_RS1_RS2(vvcfg);
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DEFINE_RS1_RS2(vtcfg);
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DISASM_INSN("vvcfgivl", vvcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg);
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DISASM_INSN("vtcfgivl", vtcfgivl, 0, xrd_reg, xrs1_reg, nxregs_reg, nfregs_reg);
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DISASM_INSN("vsetvl", vsetvl, 0, xrd_reg, xrs1_reg);
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DISASM_INSN("vf", vf, 0, xrs1_reg, imm);
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DEFINE_NOARG(fence_v_l);
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DEFINE_NOARG(fence_v_g);
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}
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