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100 lines
3.6 KiB
100 lines
3.6 KiB
// See LICENSE for license details
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#include "config.h"
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#include "vector_unit.h"
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#include "processor.h"
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#include "arith.h"
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void vectorUnit_t::vectorUnit_t::reset()
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{
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free(reg_file);
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VLEN = get_vlen();
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ELEN = get_elen();
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reg_file = malloc(NVPR * vlenb);
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memset(reg_file, 0, NVPR * vlenb);
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auto& csrmap = p->get_state()->csrmap;
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csrmap[CSR_VXSAT] = vxsat = std::make_shared<vxsat_csr_t>(p, CSR_VXSAT);
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csrmap[CSR_VSTART] = vstart = std::make_shared<vector_csr_t>(p, CSR_VSTART, /*mask*/ VLEN - 1);
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csrmap[CSR_VXRM] = vxrm = std::make_shared<vector_csr_t>(p, CSR_VXRM, /*mask*/ 0x3ul);
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csrmap[CSR_VL] = vl = std::make_shared<vector_csr_t>(p, CSR_VL, /*mask*/ 0);
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csrmap[CSR_VTYPE] = vtype = std::make_shared<vector_csr_t>(p, CSR_VTYPE, /*mask*/ 0);
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csrmap[CSR_VLENB] = std::make_shared<vector_csr_t>(p, CSR_VLENB, /*mask*/ 0, /*init*/ vlenb);
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assert(VCSR_VXSAT_SHIFT == 0); // composite_csr_t assumes vxsat begins at bit 0
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csrmap[CSR_VCSR] = std::make_shared<composite_csr_t>(p, CSR_VCSR, vxrm, vxsat, VCSR_VXRM_SHIFT);
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vtype->write_raw(0);
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set_vl(0, 0, 0, -1); // default to illegal configuration
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}
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reg_t vectorUnit_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newType)
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{
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int new_vlmul = 0;
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if (vtype->read() != newType) {
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vsew = 1 << (extract64(newType, 3, 3) + 3);
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new_vlmul = int8_t(extract64(newType, 0, 3) << 5) >> 5;
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vflmul = new_vlmul >= 0 ? 1 << new_vlmul : 1.0 / (1 << -new_vlmul);
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vlmax = (VLEN/vsew) * vflmul;
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vta = extract64(newType, 6, 1);
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vma = extract64(newType, 7, 1);
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vill = !(vflmul >= 0.125 && vflmul <= 8)
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|| vsew > std::min(vflmul, 1.0f) * ELEN
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|| (newType >> 8) != 0;
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if (vill) {
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vlmax = 0;
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vtype->write_raw(UINT64_MAX << (p->get_xlen() - 1));
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} else {
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vtype->write_raw(newType);
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}
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}
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// set vl
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if (vlmax == 0) {
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vl->write_raw(0);
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} else if (rd == 0 && rs1 == 0) {
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vl->write_raw(vl->read() > vlmax ? vlmax : vl->read());
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} else if (rd != 0 && rs1 == 0) {
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vl->write_raw(vlmax);
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} else if (rs1 != 0) {
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vl->write_raw(reqVL > vlmax ? vlmax : reqVL);
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}
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vstart->write_raw(0);
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setvl_count++;
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return vl->read();
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}
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template<class T> T& vectorUnit_t::elt(reg_t vReg, reg_t n, bool UNUSED is_write) {
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assert(vsew != 0);
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assert((VLEN >> 3)/sizeof(T) > 0);
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reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T));
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vReg += n / elts_per_reg;
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n = n % elts_per_reg;
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#ifdef WORDS_BIGENDIAN
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// "V" spec 0.7.1 requires lower indices to map to lower significant
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// bits when changing SEW, thus we need to index from the end on BE.
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n ^= elts_per_reg - 1;
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#endif
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reg_referenced[vReg] = 1;
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if (unlikely(p->get_log_commits_enabled() && is_write))
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p->get_state()->log_reg_write[((vReg) << 4) | 2] = {0, 0};
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T *regStart = (T*)((char*)reg_file + vReg * (VLEN >> 3));
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return regStart[n];
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}
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template signed char& vectorUnit_t::elt<signed char>(reg_t, reg_t, bool);
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template short& vectorUnit_t::elt<short>(reg_t, reg_t, bool);
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template int& vectorUnit_t::elt<int>(reg_t, reg_t, bool);
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template long& vectorUnit_t::elt<long>(reg_t, reg_t, bool);
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template long long& vectorUnit_t::elt<long long>(reg_t, reg_t, bool);
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template uint8_t& vectorUnit_t::elt<uint8_t>(reg_t, reg_t, bool);
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template uint16_t& vectorUnit_t::elt<uint16_t>(reg_t, reg_t, bool);
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template uint32_t& vectorUnit_t::elt<uint32_t>(reg_t, reg_t, bool);
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template uint64_t& vectorUnit_t::elt<uint64_t>(reg_t, reg_t, bool);
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template float16_t& vectorUnit_t::elt<float16_t>(reg_t, reg_t, bool);
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template float32_t& vectorUnit_t::elt<float32_t>(reg_t, reg_t, bool);
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template float64_t& vectorUnit_t::elt<float64_t>(reg_t, reg_t, bool);
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