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174 lines
7.0 KiB
174 lines
7.0 KiB
// See LICENSE for license details.
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#ifndef _RISCV_SIM_H
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#define _RISCV_SIM_H
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#include "cfg.h"
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#include "debug_module.h"
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#include "devices.h"
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#include "log_file.h"
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#include "processor.h"
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#include "simif.h"
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#include <fesvr/htif.h>
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#include <vector>
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#include <map>
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#include <unordered_map>
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#include <string>
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#include <memory>
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#include <sys/types.h>
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class mmu_t;
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class remote_bitbang_t;
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class socketif_t;
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// Type for holding a pair of device factory and device specialization arguments.
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using device_factory_sargs_t = std::pair<const device_factory_t*, std::vector<std::string>>;
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// this class encapsulates the processors and memory in a RISC-V machine.
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class sim_t : public htif_t, public simif_t
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{
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public:
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sim_t(const cfg_t *cfg, bool halted,
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std::vector<std::pair<reg_t, abstract_mem_t*>> mems,
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const std::vector<device_factory_sargs_t>& plugin_device_factories,
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const bool dtb_discovery,
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const std::vector<std::string>& args,
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const debug_module_config_t &dm_config, const char *log_path,
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bool dtb_enabled, const char *dtb_file,
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bool socket_enabled,
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FILE *cmd_file, // needed for command line option --cmd
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std::optional<unsigned long long> instruction_limit);
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~sim_t();
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int run();
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void set_debug(bool value);
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void set_histogram(bool value);
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void add_device(reg_t addr, std::shared_ptr<abstract_device_t> dev);
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// Configure logging
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//
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// If enable_log is true, an instruction trace will be generated. If
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// enable_commitlog is true, so will the commit results
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void configure_log(bool enable_log, bool enable_commitlog);
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void set_procs_debug(bool value);
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void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
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this->remote_bitbang = remote_bitbang;
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}
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const char* get_dts();
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processor_t* get_core(size_t i) { return procs.at(i); }
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abstract_interrupt_controller_t* get_intctrl() const { assert(plic.get()); return plic.get(); }
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virtual const cfg_t &get_cfg() const override { return *cfg; }
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virtual const std::map<size_t, processor_t*>& get_harts() const override { return harts; }
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const bus_t& get_bus() const { return bus;}
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// Callback for processors to let the simulation know they were reset.
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virtual void proc_reset(unsigned id) override;
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static const size_t INTERLEAVE = 5000;
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static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
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static const size_t CPU_HZ = 1000000000; // 1GHz CPU
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private:
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const cfg_t * const cfg;
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std::vector<std::pair<reg_t, abstract_mem_t*>> mems;
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std::vector<processor_t*> procs;
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std::map<size_t, processor_t*> harts;
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std::unordered_map<reg_t, char*> addr_to_mem_cache;
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std::pair<reg_t, reg_t> initrd_range;
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std::string dts;
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std::string dtb;
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bool dtb_discovery;
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bool dtb_enabled;
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std::vector<std::shared_ptr<abstract_device_t>> devices;
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std::shared_ptr<clint_t> clint;
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std::shared_ptr<plic_t> plic;
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bus_t bus;
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log_file_t log_file;
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FILE *cmd_file; // pointer to debug command input file
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std::optional<unsigned long long> instruction_limit;
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socketif_t *socketif;
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std::ostream sout_; // used for socket and terminal interface
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processor_t* get_core(const std::string& i);
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void step(size_t n); // step through simulation
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size_t current_step;
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size_t current_proc;
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bool debug;
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bool histogram_enabled; // provide a histogram of PCs
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bool log;
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remote_bitbang_t* remote_bitbang;
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std::optional<std::function<void()>> next_interactive_action;
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// If padd corresponds to memory (as opposed to an I/O device), return a
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// host pointer corresponding to paddr.
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// For these purposes, only memories that include the entire base page
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// surrounding paddr are considered; smaller memories are treated as I/O.
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virtual char* addr_to_mem(reg_t paddr) override;
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// memory-mapped I/O routines
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virtual bool mmio_load(reg_t paddr, size_t len, uint8_t* bytes) override;
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virtual bool mmio_store(reg_t paddr, size_t len, const uint8_t* bytes) override;
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void set_rom();
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virtual const char* get_symbol(uint64_t paddr) override;
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// presents a prompt for introspection into the simulation
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void interactive();
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// functions that help implement interactive()
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void interactive_help(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_quit(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
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void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_vreg(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_freg(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_fregh(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_insn(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_priv(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_dumpmems(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_mtime(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_mtimecmp(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_until(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
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void interactive_until_silent(const std::string& cmd, const std::vector<std::string>& args);
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void interactive_until_noisy(const std::string& cmd, const std::vector<std::string>& args);
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reg_t get_reg(const std::vector<std::string>& args);
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freg_t get_freg(const std::vector<std::string>& args, int size);
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reg_t get_mem(const std::vector<std::string>& args);
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reg_t get_pc(const std::vector<std::string>& args);
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reg_t get_insn(const std::vector<std::string>& args);
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friend class processor_t;
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friend class mmu_t;
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// htif
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virtual void reset() override;
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virtual void idle() override;
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virtual void read_chunk(addr_t taddr, size_t len, void* dst) override;
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virtual void write_chunk(addr_t taddr, size_t len, const void* src) override;
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virtual size_t chunk_align() override { return 8; }
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virtual size_t chunk_max_size() override { return 8; }
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virtual endianness_t get_target_endianness() const override;
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public:
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// Initialize this after procs, because in debug_module_t::reset() we
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// enumerate processors, which segfaults if procs hasn't been initialized
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// yet.
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debug_module_t debug_module;
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};
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extern volatile bool ctrlc_pressed;
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#endif
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