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108 lines
2.9 KiB
108 lines
2.9 KiB
# This code should be functional. Doesn't have to be optimal.
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# I'm writing it to prove that it can be done.
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#include "riscv/encoding.h"
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# TODO: Update these constants once they're finalized in the doc.
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#define DEBUG_RAM 0x400
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#define DEBUG_RAM_SIZE 64
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#define CLEARDEBINT 0x100
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#define SETHALTNOT 0x10c
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.global entry
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.global resume
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.global exception
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# Automatically called when Debug Mode is first entered.
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entry: j _entry
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# Should be called by Debug RAM code that has finished execution and
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# wants to return to Debug Mode.
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resume:
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j _resume
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exception:
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# Set the last word of Debug RAM to all ones, to indicate that we hit
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# an exception.
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li s0, ~0
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j _resume2
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_resume:
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li s0, 0
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_resume2:
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# Clear debug interrupt.
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csrr s1, CSR_MHARTID
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sw s1, CLEARDEBINT(zero)
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fence
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# Restore s1.
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csrr s1, CSR_MISA
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bltz s1, restore_not_32
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restore_32:
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lw s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
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j check_halt
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restore_not_32:
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slli s1, s1, 1
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bltz s1, restore_128
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restore_64:
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ld s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
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j check_halt
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restore_128:
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nop #lq s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
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# s0 contains ~0 if we got here through an exception, and 0 otherwise.
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# Store this to the last word in Debug RAM so the debugger can tell if
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# an exception occurred.
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sw s0, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
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check_halt:
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csrr s0, CSR_DCSR
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andi s0, s0, DCSR_HALT
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beqz s0, exit
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j wait_for_interrupt
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exit:
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# Restore s0.
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csrr s0, CSR_DSCRATCH
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dret
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_entry:
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# Save s0 in DSCRATCH
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csrw CSR_DSCRATCH, s0
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# Check why we're here
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csrr s0, CSR_DCSR
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# cause is in bits 8:6 of dcsr
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andi s0, s0, DCSR_CAUSE
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addi s0, s0, -(DCSR_CAUSE_DEBUGINT<<6)
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bnez s0, spontaneous_halt
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jdebugram:
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# Save s1 so that the debug program can use two registers.
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fence.i
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csrr s0, CSR_MISA
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bltz s0, save_not_32
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save_32:
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sw s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
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jr zero, DEBUG_RAM
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save_not_32:
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slli s0, s0, 1
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bltz s0, save_128
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save_64:
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sd s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
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jr zero, DEBUG_RAM
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save_128:
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nop #sq s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
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jr zero, DEBUG_RAM
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spontaneous_halt:
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csrr s0, CSR_MHARTID
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sw s0, SETHALTNOT(zero)
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csrsi CSR_DCSR, DCSR_HALT
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wait_for_interrupt:
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csrr s0, CSR_DCSR
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andi s0, s0, DCSR_DEBUGINT
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beqz s0, wait_for_interrupt
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j jdebugram
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