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1382 lines
17 KiB
1382 lines
17 KiB
get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
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get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
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riscv_subproject_deps = \
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fdt \
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disasm \
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fesvr \
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softfloat \
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riscv_CFLAGS = -fPIC
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riscv_install_shared_lib = yes
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riscv_install_pcs = yes
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riscv_install_prog_srcs = \
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riscv_install_hdrs = \
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abstract_device.h \
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abstract_interrupt_controller.h \
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cachesim.h \
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cfg.h \
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common.h \
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csrs.h \
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debug_defines.h \
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debug_module.h \
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debug_rom_defines.h \
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decode.h \
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devices.h \
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disasm.h \
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encoding.h \
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entropy_source.h \
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extension.h \
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isa_parser.h \
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log_file.h \
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memtracer.h \
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mmio_plugin.h \
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mmu.h \
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platform.h \
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processor.h \
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rocc.h \
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sim.h \
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simif.h \
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trap.h \
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triggers.h \
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vector_unit.h \
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riscv_precompiled_hdrs = \
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insn_template.h \
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riscv_srcs = \
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isa_parser.cc \
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processor.cc \
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execute.cc \
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dts.cc \
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sim.cc \
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interactive.cc \
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cachesim.cc \
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mmu.cc \
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extension.cc \
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extensions.cc \
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rocc.cc \
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devices.cc \
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rom.cc \
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clint.cc \
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plic.cc \
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ns16550.cc \
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debug_module.cc \
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remote_bitbang.cc \
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jtag_dtm.cc \
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csrs.cc \
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triggers.cc \
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vector_unit.cc \
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socketif.cc \
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cfg.cc \
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$(riscv_gen_srcs) \
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riscv_test_srcs = \
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check-opcode-overlap.t.cc \
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riscv_gen_hdrs = \
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insn_list.h \
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riscv_insn_ext_i = \
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add \
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addi \
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addiw \
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addw \
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and \
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andi \
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auipc \
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beq \
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bge \
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bgeu \
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blt \
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bltu \
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bne \
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jal \
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jalr \
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lb \
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lbu \
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ld \
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lh \
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lhu \
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lui \
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lw \
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lwu \
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or \
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ori \
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sb \
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sd \
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sh \
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sll \
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slli \
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slliw \
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sllw \
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slt \
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slti \
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sltiu \
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sltu \
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sra \
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srai \
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sraiw \
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sraw \
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srl \
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srli \
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srliw \
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srlw \
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sub \
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subw \
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sw \
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xor \
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xori \
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fence \
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fence_i \
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riscv_insn_ext_a = \
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amoadd_d \
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amoadd_w \
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amoand_d \
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amoand_w \
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amomax_d \
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amomaxu_d \
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amomaxu_w \
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amomax_w \
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amomin_d \
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amominu_d \
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amominu_w \
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amomin_w \
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amoor_d \
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amoor_w \
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amoswap_d \
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amoswap_w \
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amoxor_d \
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amoxor_w \
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lr_d \
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lr_w \
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sc_d \
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sc_w \
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riscv_insn_ext_c = \
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c_add \
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c_addi \
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c_addi4spn \
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c_addw \
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c_and \
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c_andi \
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c_beqz \
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c_bnez \
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c_ebreak \
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c_fld \
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c_fldsp \
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c_flw \
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c_flwsp \
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c_fsd \
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c_fsdsp \
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c_fsw \
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c_fswsp \
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c_j \
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c_jal \
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c_jalr \
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c_jr \
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c_li \
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c_lui \
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c_lw \
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c_lwsp \
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c_mv \
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c_or \
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c_slli \
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c_srai \
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c_srli \
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c_sub \
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c_subw \
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c_sw \
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c_swsp \
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c_xor \
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riscv_insn_ext_m = \
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div \
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divu \
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divuw \
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divw \
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mul \
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mulh \
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mulhsu \
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mulhu \
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mulw \
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rem \
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remu \
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remuw \
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remw \
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riscv_insn_ext_f = \
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fadd_s \
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fclass_s \
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fcvt_l_s \
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fcvt_lu_s \
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fcvt_s_l \
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fcvt_s_lu \
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fcvt_s_w \
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fcvt_s_wu \
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fcvt_w_s \
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fcvt_wu_s \
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fdiv_s \
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feq_s \
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fle_s \
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flt_s \
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flw \
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fmadd_s \
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fmax_s \
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fmin_s \
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fmsub_s \
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fmul_s \
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fmv_w_x \
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fmv_x_w \
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fnmadd_s \
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fnmsub_s \
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fsgnj_s \
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fsgnjn_s \
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fsgnjx_s \
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fsqrt_s \
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fsub_s \
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fsw \
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riscv_insn_ext_f_zfa= \
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fli_s \
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fmaxm_s \
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fminm_s \
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fround_s \
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froundnx_s \
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fleq_s \
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fltq_s
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riscv_insn_ext_d = \
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fadd_d \
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fclass_d \
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fcvt_d_l \
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fcvt_d_lu \
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fcvt_d_q \
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fcvt_d_s \
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fcvt_d_w \
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fcvt_d_wu \
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fcvt_l_d \
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fcvt_lu_d \
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fcvt_s_d \
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fcvt_w_d \
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fcvt_wu_d \
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fdiv_d \
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feq_d \
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fld \
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fle_d \
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flt_d \
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fmadd_d \
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fmax_d \
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fmin_d \
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fmsub_d \
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fmul_d \
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fmv_d_x \
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fmv_x_d \
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fnmadd_d \
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fnmsub_d \
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fsd \
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fsgnj_d \
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fsgnjn_d \
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fsgnjx_d \
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fsqrt_d \
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fsub_d \
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riscv_insn_ext_d_zfa = \
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fli_d \
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fmaxm_d \
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fminm_d \
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fround_d \
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froundnx_d \
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fmvh_x_d \
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fmvp_d_x \
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fcvtmod_w_d \
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fleq_d \
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fltq_d
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riscv_insn_ext_zfh = \
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fadd_h \
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fclass_h \
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fcvt_l_h \
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fcvt_lu_h \
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fcvt_d_h \
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fcvt_h_d \
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fcvt_h_l \
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fcvt_h_lu \
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fcvt_h_q \
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fcvt_h_s \
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fcvt_h_w \
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fcvt_h_wu \
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fcvt_q_h \
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fcvt_s_h \
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fcvt_w_h \
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fcvt_wu_h \
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fdiv_h \
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feq_h \
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fle_h \
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flh \
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flt_h \
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fmadd_h \
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fmax_h \
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fmin_h \
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fmsub_h \
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fmul_h \
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fmv_h_x \
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fmv_x_h \
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fnmadd_h \
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fnmsub_h \
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fsgnj_h \
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fsgnjn_h \
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fsgnjx_h \
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fsh \
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fsqrt_h \
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fsub_h \
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riscv_insn_ext_zfh_zfa = \
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fli_h \
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fmaxm_h \
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fminm_h \
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fround_h \
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froundnx_h \
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fleq_h \
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fltq_h
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riscv_insn_ext_q = \
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fadd_q \
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fclass_q \
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fcvt_l_q \
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fcvt_lu_q \
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fcvt_q_d \
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fcvt_q_l \
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fcvt_q_lu \
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fcvt_q_s \
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fcvt_q_w \
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fcvt_q_wu \
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fcvt_s_q \
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fcvt_w_q \
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fcvt_wu_q \
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fdiv_q \
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feq_q \
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fle_q \
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flq \
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flt_q \
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fmadd_q \
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fmax_q \
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fmin_q \
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fmsub_q \
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fmul_q \
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fnmadd_q \
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fnmsub_q \
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fsgnj_q \
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fsgnjn_q \
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fsgnjx_q \
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fsq \
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fsqrt_q \
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fsub_q \
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riscv_insn_ext_q_zfa = \
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fli_q \
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fmaxm_q \
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fminm_q \
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fround_q \
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froundnx_q \
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fmvh_x_q \
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fmvp_q_x \
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fleq_q \
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fltq_q
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riscv_insn_ext_b = \
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add_uw \
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andn \
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sh1add \
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sh1add_uw \
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sh2add \
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sh2add_uw \
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sh3add \
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sh3add_uw \
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clmul \
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clmulh \
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clmulr \
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clz \
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clzw \
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cmix \
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ctz \
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ctzw \
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fsr \
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fsri \
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fsrw \
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gorci \
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grevi \
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max \
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maxu \
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min \
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minu \
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orn \
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pack \
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packh \
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packu \
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packw \
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cpop \
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cpopw \
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rol \
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rolw \
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ror \
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rori \
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roriw \
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rorw \
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bclr \
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bclri \
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bext \
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bexti \
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binv \
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binvi \
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bset \
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bseti \
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sext_b \
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sext_h \
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shfli \
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slli_uw \
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unshfli \
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xnor \
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xperm4 \
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xperm8 \
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# Scalar Crypto ISE
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riscv_insn_ext_k = \
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aes32dsi \
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aes32dsmi \
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aes32esi \
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aes32esmi \
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aes64ds \
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aes64dsm \
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aes64es \
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aes64esm \
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aes64ks1i \
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aes64ks2 \
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aes64im \
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sha256sig0 \
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sha256sig1 \
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sha256sum0 \
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sha256sum1 \
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sha512sig0 \
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sha512sig0h \
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sha512sig0l \
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sha512sig1 \
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sha512sig1h \
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sha512sig1l \
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sha512sum0 \
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sha512sum0r \
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sha512sum1 \
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sha512sum1r \
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sm3p0 \
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sm3p1 \
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sm4ed \
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sm4ks
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riscv_insn_ext_v_alu_int = \
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vaadd_vv \
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vaaddu_vv \
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vaadd_vx \
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vaaddu_vx \
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vadc_vim \
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vadc_vvm \
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vadc_vxm \
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vadd_vi \
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vadd_vv \
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vadd_vx \
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vand_vi \
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vand_vv \
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vand_vx \
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vasub_vv \
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vasubu_vv \
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vasub_vx \
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vasubu_vx \
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vcompress_vm \
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vcpop_m \
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vdiv_vv \
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vdiv_vx \
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vdivu_vv \
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vdivu_vx \
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vid_v \
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viota_m \
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vmacc_vv \
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vmacc_vx \
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vmadc_vv \
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vmadc_vx \
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vmadc_vi \
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vmadc_vim \
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vmadc_vvm \
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vmadc_vxm \
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vmadd_vv \
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vmadd_vx \
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vmand_mm \
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vmandn_mm \
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vmax_vv \
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vmax_vx \
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vmaxu_vv \
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vmaxu_vx \
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vmerge_vim \
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vmerge_vvm \
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vmerge_vxm \
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vfirst_m \
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vmin_vv \
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vmin_vx \
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vminu_vv \
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vminu_vx \
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vmnand_mm \
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vmnor_mm \
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vmor_mm \
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vmorn_mm \
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vmsbc_vv \
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vmsbc_vx \
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vmsbc_vvm \
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vmsbc_vxm \
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vmsbf_m \
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vmseq_vi \
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vmseq_vv \
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vmseq_vx \
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vmsgt_vi \
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vmsgt_vx \
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vmsgtu_vi \
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vmsgtu_vx \
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vmsif_m \
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vmsle_vi \
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vmsle_vv \
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vmsle_vx \
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vmsleu_vi \
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vmsleu_vv \
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vmsleu_vx \
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vmslt_vv \
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vmslt_vx \
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vmsltu_vv \
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vmsltu_vx \
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vmsne_vi \
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vmsne_vv \
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vmsne_vx \
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vmsof_m \
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vmul_vv \
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vmul_vx \
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vmulh_vv \
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vmulh_vx \
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vmulhsu_vv \
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vmulhsu_vx \
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vmulhu_vv \
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vmulhu_vx \
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vmv_s_x \
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vmv_v_i \
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vmv_v_v \
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vmv_v_x \
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vmv_x_s \
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vmv1r_v \
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vmv2r_v \
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vmv4r_v \
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vmv8r_v \
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vmxnor_mm \
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vmxor_mm \
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vnclip_wi \
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vnclip_wv \
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vnclip_wx \
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vnclipu_wi \
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vnclipu_wv \
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vnclipu_wx \
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vnmsac_vv \
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vnmsac_vx \
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vnmsub_vv \
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vnmsub_vx \
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vnsra_wi \
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vnsra_wv \
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vnsra_wx \
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vnsrl_wi \
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vnsrl_wv \
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vnsrl_wx \
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vor_vi \
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vor_vv \
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vor_vx \
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vredand_vs \
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vredmax_vs \
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vredmaxu_vs \
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vredmin_vs \
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vredminu_vs \
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vredor_vs \
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vredsum_vs \
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vredxor_vs \
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vrem_vv \
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vrem_vx \
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vremu_vv \
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vremu_vx \
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vrgather_vi \
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vrgather_vv \
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vrgather_vx \
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vrgatherei16_vv \
|
|
vrsub_vi \
|
|
vrsub_vx \
|
|
vsadd_vi \
|
|
vsadd_vv \
|
|
vsadd_vx \
|
|
vsaddu_vi \
|
|
vsaddu_vv \
|
|
vsaddu_vx \
|
|
vsbc_vvm \
|
|
vsbc_vxm \
|
|
vsext_vf2 \
|
|
vsext_vf4 \
|
|
vsext_vf8 \
|
|
vslide1down_vx \
|
|
vslide1up_vx \
|
|
vslidedown_vi \
|
|
vslidedown_vx \
|
|
vslideup_vi \
|
|
vslideup_vx \
|
|
vsll_vi \
|
|
vsll_vv \
|
|
vsll_vx \
|
|
vsmul_vv \
|
|
vsmul_vx \
|
|
vsra_vi \
|
|
vsra_vv \
|
|
vsra_vx \
|
|
vsrl_vi \
|
|
vsrl_vv \
|
|
vsrl_vx \
|
|
vssra_vi \
|
|
vssra_vv \
|
|
vssra_vx \
|
|
vssrl_vi \
|
|
vssrl_vv \
|
|
vssrl_vx \
|
|
vssub_vv \
|
|
vssub_vx \
|
|
vssubu_vv \
|
|
vssubu_vx \
|
|
vsub_vv \
|
|
vsub_vx \
|
|
vwadd_vv \
|
|
vwadd_vx \
|
|
vwadd_wv \
|
|
vwadd_wx \
|
|
vwaddu_vv \
|
|
vwaddu_vx \
|
|
vwaddu_wv \
|
|
vwaddu_wx \
|
|
vwmacc_vv \
|
|
vwmacc_vx \
|
|
vwmaccsu_vv \
|
|
vwmaccsu_vx \
|
|
vwmaccu_vv \
|
|
vwmaccu_vx \
|
|
vwmaccus_vx \
|
|
vwmul_vv \
|
|
vwmul_vx \
|
|
vwmulsu_vv \
|
|
vwmulsu_vx \
|
|
vwmulu_vv \
|
|
vwmulu_vx \
|
|
vwredsum_vs \
|
|
vwredsumu_vs \
|
|
vwsub_vv \
|
|
vwsub_vx \
|
|
vwsub_wv \
|
|
vwsub_wx \
|
|
vwsubu_vv \
|
|
vwsubu_vx \
|
|
vwsubu_wv \
|
|
vwsubu_wx \
|
|
vxor_vi \
|
|
vxor_vv \
|
|
vxor_vx \
|
|
vzext_vf2 \
|
|
vzext_vf4 \
|
|
vzext_vf8 \
|
|
|
|
riscv_insn_ext_v_alu_fp = \
|
|
vfadd_vf \
|
|
vfadd_vv \
|
|
vfclass_v \
|
|
vfcvt_f_x_v \
|
|
vfcvt_f_xu_v \
|
|
vfcvt_rtz_x_f_v \
|
|
vfcvt_rtz_xu_f_v \
|
|
vfcvt_x_f_v \
|
|
vfcvt_xu_f_v \
|
|
vfdiv_vf \
|
|
vfdiv_vv \
|
|
vfmacc_vf \
|
|
vfmacc_vv \
|
|
vfmadd_vf \
|
|
vfmadd_vv \
|
|
vfmax_vf \
|
|
vfmax_vv \
|
|
vfmerge_vfm \
|
|
vfmin_vf \
|
|
vfmin_vv \
|
|
vfmsac_vf \
|
|
vfmsac_vv \
|
|
vfmsub_vf \
|
|
vfmsub_vv \
|
|
vfmul_vf \
|
|
vfmul_vv \
|
|
vfmv_f_s \
|
|
vfmv_s_f \
|
|
vfmv_v_f \
|
|
vfncvt_f_f_w \
|
|
vfncvt_f_x_w \
|
|
vfncvt_f_xu_w \
|
|
vfncvt_rod_f_f_w \
|
|
vfncvt_rtz_x_f_w \
|
|
vfncvt_rtz_xu_f_w \
|
|
vfncvt_x_f_w \
|
|
vfncvt_xu_f_w \
|
|
vfnmacc_vf \
|
|
vfnmacc_vv \
|
|
vfnmadd_vf \
|
|
vfnmadd_vv \
|
|
vfnmsac_vf \
|
|
vfnmsac_vv \
|
|
vfnmsub_vf \
|
|
vfnmsub_vv \
|
|
vfrdiv_vf \
|
|
vfredmax_vs \
|
|
vfredmin_vs \
|
|
vfredosum_vs \
|
|
vfredusum_vs \
|
|
vfrec7_v \
|
|
vfrsub_vf \
|
|
vfrsqrt7_v \
|
|
vfsgnj_vf \
|
|
vfsgnj_vv \
|
|
vfsgnjn_vf \
|
|
vfsgnjn_vv \
|
|
vfsgnjx_vf \
|
|
vfsgnjx_vv \
|
|
vfsqrt_v \
|
|
vfslide1down_vf \
|
|
vfslide1up_vf \
|
|
vfsub_vf \
|
|
vfsub_vv \
|
|
vfwadd_vf \
|
|
vfwadd_vv \
|
|
vfwadd_wf \
|
|
vfwadd_wv \
|
|
vfwcvt_f_f_v \
|
|
vfwcvt_f_x_v \
|
|
vfwcvt_f_xu_v \
|
|
vfwcvt_rtz_x_f_v \
|
|
vfwcvt_rtz_xu_f_v \
|
|
vfwcvt_x_f_v \
|
|
vfwcvt_xu_f_v \
|
|
vfwmacc_vf \
|
|
vfwmacc_vv \
|
|
vfwmsac_vf \
|
|
vfwmsac_vv \
|
|
vfwmul_vf \
|
|
vfwmul_vv \
|
|
vfwnmacc_vf \
|
|
vfwnmacc_vv \
|
|
vfwnmsac_vf \
|
|
vfwnmsac_vv \
|
|
vfwredosum_vs \
|
|
vfwredusum_vs \
|
|
vfwsub_vf \
|
|
vfwsub_vv \
|
|
vfwsub_wf \
|
|
vfwsub_wv \
|
|
vmfeq_vf \
|
|
vmfeq_vv \
|
|
vmfge_vf \
|
|
vmfgt_vf \
|
|
vmfle_vf \
|
|
vmfle_vv \
|
|
vmflt_vf \
|
|
vmflt_vv \
|
|
vmfne_vf \
|
|
vmfne_vv \
|
|
|
|
riscv_insn_ext_v_amo = \
|
|
vamoswapei8_v \
|
|
vamoaddei8_v \
|
|
vamoandei8_v \
|
|
vamomaxei8_v \
|
|
vamomaxuei8_v \
|
|
vamominei8_v \
|
|
vamominuei8_v \
|
|
vamoorei8_v \
|
|
vamoxorei8_v \
|
|
vamoswapei16_v \
|
|
vamoaddei16_v \
|
|
vamoandei16_v \
|
|
vamomaxei16_v \
|
|
vamomaxuei16_v \
|
|
vamominei16_v \
|
|
vamominuei16_v \
|
|
vamoorei16_v \
|
|
vamoxorei16_v \
|
|
vamoswapei32_v \
|
|
vamoaddei32_v \
|
|
vamoandei32_v \
|
|
vamomaxei32_v \
|
|
vamomaxuei32_v \
|
|
vamominei32_v \
|
|
vamominuei32_v \
|
|
vamoorei32_v \
|
|
vamoxorei32_v \
|
|
vamoswapei64_v \
|
|
vamoaddei64_v \
|
|
vamoandei64_v \
|
|
vamomaxei64_v \
|
|
vamomaxuei64_v \
|
|
vamominei64_v \
|
|
vamominuei64_v \
|
|
vamoorei64_v \
|
|
vamoxorei64_v \
|
|
|
|
riscv_insn_ext_v_ldst = \
|
|
vlm_v \
|
|
vle8_v \
|
|
vle16_v \
|
|
vle32_v \
|
|
vle64_v \
|
|
vloxei8_v \
|
|
vloxei16_v \
|
|
vloxei32_v \
|
|
vloxei64_v \
|
|
vlse8_v \
|
|
vlse16_v \
|
|
vlse32_v \
|
|
vlse64_v \
|
|
vluxei8_v \
|
|
vluxei16_v \
|
|
vluxei32_v \
|
|
vluxei64_v \
|
|
vle8ff_v \
|
|
vle16ff_v \
|
|
vle32ff_v \
|
|
vle64ff_v \
|
|
vl1re8_v \
|
|
vl2re8_v \
|
|
vl4re8_v \
|
|
vl8re8_v \
|
|
vl1re16_v \
|
|
vl2re16_v \
|
|
vl4re16_v \
|
|
vl8re16_v \
|
|
vl1re32_v \
|
|
vl2re32_v \
|
|
vl4re32_v \
|
|
vl8re32_v \
|
|
vl1re64_v \
|
|
vl2re64_v \
|
|
vl4re64_v \
|
|
vl8re64_v \
|
|
vsm_v \
|
|
vse8_v \
|
|
vse16_v \
|
|
vse32_v \
|
|
vse64_v \
|
|
vsse8_v \
|
|
vsoxei8_v \
|
|
vsoxei16_v \
|
|
vsoxei32_v \
|
|
vsoxei64_v \
|
|
vsse16_v \
|
|
vsse32_v \
|
|
vsse64_v \
|
|
vsuxei8_v \
|
|
vsuxei16_v \
|
|
vsuxei32_v \
|
|
vsuxei64_v \
|
|
vs1r_v \
|
|
vs2r_v \
|
|
vs4r_v \
|
|
vs8r_v \
|
|
|
|
riscv_insn_ext_v_ctrl = \
|
|
vsetivli \
|
|
vsetvli \
|
|
vsetvl \
|
|
|
|
riscv_insn_ext_v = \
|
|
$(riscv_insn_ext_v_alu_fp) \
|
|
$(riscv_insn_ext_v_alu_int) \
|
|
$(riscv_insn_ext_v_amo) \
|
|
$(riscv_insn_ext_v_ctrl) \
|
|
$(riscv_insn_ext_v_ldst) \
|
|
|
|
riscv_insn_ext_h = \
|
|
hfence_gvma \
|
|
hfence_vvma \
|
|
hlv_b \
|
|
hlv_bu \
|
|
hlv_h \
|
|
hlv_hu \
|
|
hlvx_hu \
|
|
hlv_w \
|
|
hlv_wu \
|
|
hlvx_wu \
|
|
hlv_d \
|
|
hsv_b \
|
|
hsv_h \
|
|
hsv_w \
|
|
hsv_d \
|
|
|
|
riscv_insn_ext_p_simd = \
|
|
add16 \
|
|
radd16 \
|
|
uradd16 \
|
|
kadd16 \
|
|
ukadd16 \
|
|
sub16 \
|
|
rsub16 \
|
|
ursub16 \
|
|
ksub16 \
|
|
uksub16 \
|
|
cras16 \
|
|
rcras16 \
|
|
urcras16 \
|
|
kcras16 \
|
|
ukcras16 \
|
|
crsa16 \
|
|
rcrsa16 \
|
|
urcrsa16 \
|
|
kcrsa16 \
|
|
ukcrsa16 \
|
|
stas16 \
|
|
rstas16 \
|
|
urstas16 \
|
|
kstas16 \
|
|
ukstas16 \
|
|
stsa16 \
|
|
rstsa16 \
|
|
urstsa16 \
|
|
kstsa16 \
|
|
ukstsa16 \
|
|
add8 \
|
|
radd8 \
|
|
uradd8 \
|
|
kadd8 \
|
|
ukadd8 \
|
|
sub8 \
|
|
rsub8 \
|
|
ursub8 \
|
|
ksub8 \
|
|
uksub8 \
|
|
sra16 \
|
|
srai16 \
|
|
sra16_u \
|
|
srai16_u \
|
|
srl16 \
|
|
srli16 \
|
|
srl16_u \
|
|
srli16_u \
|
|
sll16 \
|
|
slli16 \
|
|
ksll16 \
|
|
kslli16 \
|
|
kslra16 \
|
|
kslra16_u \
|
|
sra8 \
|
|
srai8 \
|
|
sra8_u \
|
|
srai8_u \
|
|
srl8 \
|
|
srli8 \
|
|
srl8_u \
|
|
srli8_u \
|
|
sll8 \
|
|
slli8 \
|
|
ksll8 \
|
|
kslli8 \
|
|
kslra8 \
|
|
kslra8_u \
|
|
cmpeq16 \
|
|
scmplt16 \
|
|
scmple16 \
|
|
ucmplt16 \
|
|
ucmple16 \
|
|
cmpeq8 \
|
|
scmplt8 \
|
|
scmple8 \
|
|
ucmplt8 \
|
|
ucmple8 \
|
|
smul16 \
|
|
smulx16 \
|
|
umul16 \
|
|
umulx16 \
|
|
khm16 \
|
|
khmx16 \
|
|
smul8 \
|
|
smulx8 \
|
|
umul8 \
|
|
umulx8 \
|
|
khm8 \
|
|
khmx8 \
|
|
smin16 \
|
|
umin16 \
|
|
smax16 \
|
|
umax16 \
|
|
sclip16 \
|
|
uclip16 \
|
|
kabs16 \
|
|
clrs16 \
|
|
clz16 \
|
|
smin8 \
|
|
umin8 \
|
|
smax8 \
|
|
umax8 \
|
|
sclip8 \
|
|
uclip8 \
|
|
kabs8 \
|
|
clrs8 \
|
|
clz8 \
|
|
sunpkd810 \
|
|
sunpkd820 \
|
|
sunpkd830 \
|
|
sunpkd831 \
|
|
sunpkd832 \
|
|
zunpkd810 \
|
|
zunpkd820 \
|
|
zunpkd830 \
|
|
zunpkd831 \
|
|
zunpkd832 \
|
|
|
|
riscv_insn_ext_p_partial_simd = \
|
|
pkbb16 \
|
|
pkbt16 \
|
|
pktb16 \
|
|
pktt16 \
|
|
smmul \
|
|
smmul_u \
|
|
kmmac \
|
|
kmmac_u \
|
|
kmmsb \
|
|
kmmsb_u \
|
|
kwmmul \
|
|
kwmmul_u \
|
|
smmwb \
|
|
smmwb_u \
|
|
smmwt \
|
|
smmwt_u \
|
|
kmmawb \
|
|
kmmawb_u \
|
|
kmmawt \
|
|
kmmawt_u \
|
|
kmmwb2 \
|
|
kmmwb2_u \
|
|
kmmwt2 \
|
|
kmmwt2_u \
|
|
kmmawb2 \
|
|
kmmawb2_u \
|
|
kmmawt2 \
|
|
kmmawt2_u \
|
|
smbb16 \
|
|
smbt16 \
|
|
smtt16 \
|
|
kmda \
|
|
kmxda \
|
|
smds \
|
|
smdrs \
|
|
smxds \
|
|
kmabb \
|
|
kmabt \
|
|
kmatt \
|
|
kmada \
|
|
kmaxda \
|
|
kmads \
|
|
kmadrs \
|
|
kmaxds \
|
|
kmsda \
|
|
kmsxda \
|
|
smal \
|
|
sclip32 \
|
|
uclip32 \
|
|
clrs32 \
|
|
pbsad \
|
|
pbsada \
|
|
smaqa \
|
|
umaqa \
|
|
smaqa_su \
|
|
|
|
riscv_insn_ext_p_64_bit_profile = \
|
|
add64 \
|
|
radd64 \
|
|
uradd64 \
|
|
kadd64 \
|
|
ukadd64 \
|
|
sub64 \
|
|
rsub64 \
|
|
ursub64 \
|
|
ksub64 \
|
|
uksub64 \
|
|
smar64 \
|
|
smsr64 \
|
|
umar64 \
|
|
umsr64 \
|
|
kmar64 \
|
|
kmsr64 \
|
|
ukmar64 \
|
|
ukmsr64 \
|
|
smalbb \
|
|
smalbt \
|
|
smaltt \
|
|
smalda \
|
|
smalxda \
|
|
smalds \
|
|
smaldrs \
|
|
smalxds \
|
|
smslda \
|
|
smslxda \
|
|
|
|
riscv_insn_ext_p_non_simd = \
|
|
kaddh \
|
|
ksubh \
|
|
khmbb \
|
|
khmbt \
|
|
khmtt \
|
|
ukaddh \
|
|
uksubh \
|
|
kaddw \
|
|
ukaddw \
|
|
ksubw \
|
|
uksubw \
|
|
kdmbb \
|
|
kdmbt \
|
|
kdmtt \
|
|
kslraw \
|
|
kslraw_u \
|
|
ksllw \
|
|
kslliw \
|
|
kdmabb \
|
|
kdmabt \
|
|
kdmatt \
|
|
kabsw \
|
|
raddw \
|
|
uraddw \
|
|
rsubw \
|
|
ursubw \
|
|
mulr64 \
|
|
mulsr64 \
|
|
msubr32 \
|
|
ave \
|
|
sra_u \
|
|
srai_u \
|
|
insb \
|
|
maddr32 \
|
|
|
|
riscv_insn_ext_p_rv64_only = \
|
|
add32 \
|
|
radd32 \
|
|
uradd32 \
|
|
kadd32 \
|
|
ukadd32 \
|
|
sub32 \
|
|
rsub32 \
|
|
ursub32 \
|
|
ksub32 \
|
|
uksub32 \
|
|
cras32 \
|
|
rcras32 \
|
|
urcras32 \
|
|
kcras32 \
|
|
ukcras32 \
|
|
crsa32 \
|
|
rcrsa32 \
|
|
urcrsa32 \
|
|
kcrsa32 \
|
|
ukcrsa32 \
|
|
stas32 \
|
|
rstas32 \
|
|
urstas32 \
|
|
kstas32 \
|
|
ukstas32 \
|
|
stsa32 \
|
|
rstsa32 \
|
|
urstsa32 \
|
|
kstsa32 \
|
|
ukstsa32 \
|
|
sra32 \
|
|
srai32 \
|
|
sra32_u \
|
|
srai32_u \
|
|
srl32 \
|
|
srli32 \
|
|
srl32_u \
|
|
srli32_u \
|
|
sll32 \
|
|
slli32 \
|
|
ksll32 \
|
|
kslli32 \
|
|
kslra32 \
|
|
kslra32_u \
|
|
smin32 \
|
|
umin32 \
|
|
smax32 \
|
|
umax32 \
|
|
kabs32 \
|
|
khmbb16 \
|
|
khmbt16 \
|
|
khmtt16 \
|
|
kdmbb16 \
|
|
kdmbt16 \
|
|
kdmtt16 \
|
|
kdmabb16 \
|
|
kdmabt16 \
|
|
kdmatt16 \
|
|
smbt32 \
|
|
smtt32 \
|
|
kmabb32 \
|
|
kmabt32 \
|
|
kmatt32 \
|
|
kmda32 \
|
|
kmxda32 \
|
|
kmaxda32 \
|
|
kmads32 \
|
|
kmadrs32 \
|
|
kmaxds32 \
|
|
kmsda32 \
|
|
kmsxda32 \
|
|
smds32 \
|
|
smdrs32 \
|
|
smxds32 \
|
|
sraiw_u \
|
|
pkbt32 \
|
|
pktb32 \
|
|
clz32 \
|
|
|
|
riscv_insn_ext_p = \
|
|
$(riscv_insn_ext_p_simd) \
|
|
$(riscv_insn_ext_p_partial_simd) \
|
|
$(riscv_insn_ext_p_64_bit_profile) \
|
|
$(riscv_insn_ext_p_non_simd) \
|
|
$(riscv_insn_ext_p_rv64_only) \
|
|
|
|
riscv_insn_priv = \
|
|
csrrc \
|
|
csrrci \
|
|
csrrs \
|
|
csrrsi \
|
|
csrrw \
|
|
csrrwi \
|
|
dret \
|
|
ebreak \
|
|
ecall \
|
|
mret \
|
|
sfence_vma \
|
|
sret \
|
|
wfi \
|
|
|
|
riscv_insn_smrnmi = \
|
|
mnret \
|
|
|
|
riscv_insn_svinval = \
|
|
sfence_w_inval \
|
|
sfence_inval_ir \
|
|
sinval_vma \
|
|
hinval_vvma \
|
|
hinval_gvma \
|
|
|
|
riscv_insn_ext_zcb = \
|
|
c_zext_b \
|
|
c_zext_h \
|
|
c_zext_w \
|
|
c_sext_b \
|
|
c_sext_h \
|
|
c_not \
|
|
c_mul \
|
|
c_lbu \
|
|
c_lhu \
|
|
c_lh \
|
|
c_sb \
|
|
c_sh \
|
|
|
|
riscv_insn_ext_zcmp = \
|
|
cm_push \
|
|
cm_pop \
|
|
cm_popret \
|
|
cm_popretz \
|
|
cm_mva01s \
|
|
cm_mvsa01 \
|
|
|
|
riscv_insn_ext_zcmt = \
|
|
cm_jalt \
|
|
|
|
riscv_insn_ext_zce = \
|
|
$(riscv_insn_ext_zcb) \
|
|
$(riscv_insn_ext_zcmp) \
|
|
$(riscv_insn_ext_zcmt) \
|
|
|
|
riscv_insn_ext_cmo = \
|
|
cbo_clean \
|
|
cbo_flush \
|
|
cbo_inval \
|
|
cbo_zero \
|
|
|
|
riscv_insn_ext_zicond = \
|
|
czero_eqz \
|
|
czero_nez \
|
|
|
|
riscv_insn_ext_zfbfmin = \
|
|
fcvt_bf16_s \
|
|
fcvt_s_bf16 \
|
|
|
|
riscv_insn_ext_zvfbfmin = \
|
|
vfncvtbf16_f_f_w \
|
|
vfwcvtbf16_f_f_v \
|
|
|
|
riscv_insn_ext_zvfbfwma = \
|
|
vfwmaccbf16_vv \
|
|
vfwmaccbf16_vf \
|
|
|
|
riscv_insn_ext_bf16 = \
|
|
$(riscv_insn_ext_zfbfmin) \
|
|
$(riscv_insn_ext_zvfbfmin) \
|
|
$(riscv_insn_ext_zvfbfwma) \
|
|
|
|
riscv_insn_ext_zacas = \
|
|
amocas_w \
|
|
amocas_d \
|
|
$(if $(HAVE_INT128),amocas_q)
|
|
|
|
riscv_insn_list = \
|
|
$(riscv_insn_ext_a) \
|
|
$(riscv_insn_ext_c) \
|
|
$(riscv_insn_ext_i) \
|
|
$(riscv_insn_ext_m) \
|
|
$(riscv_insn_ext_f) \
|
|
$(riscv_insn_ext_f_zfa) \
|
|
$(riscv_insn_ext_d) \
|
|
$(riscv_insn_ext_d_zfa) \
|
|
$(riscv_insn_ext_zfh) \
|
|
$(riscv_insn_ext_zfh_zfa) \
|
|
$(riscv_insn_ext_q) \
|
|
$(riscv_insn_ext_q_zfa) \
|
|
$(riscv_insn_ext_b) \
|
|
$(riscv_insn_ext_k) \
|
|
$(if $(HAVE_INT128),$(riscv_insn_ext_v),) \
|
|
$(riscv_insn_ext_zce) \
|
|
$(riscv_insn_ext_h) \
|
|
$(riscv_insn_ext_p) \
|
|
$(riscv_insn_priv) \
|
|
$(riscv_insn_svinval) \
|
|
$(riscv_insn_smrnmi) \
|
|
$(riscv_insn_ext_cmo) \
|
|
$(riscv_insn_ext_zicond) \
|
|
$(riscv_insn_ext_bf16) \
|
|
$(riscv_insn_ext_zacas) \
|
|
|
|
riscv_gen_srcs = $(addsuffix .cc,$(riscv_insn_list))
|
|
|
|
insn_list.h: $(src_dir)/riscv/riscv.mk.in
|
|
for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \
|
|
printf 'DEFINE_INSN(%s)\n' "$${insn}" ; \
|
|
done > $@.tmp
|
|
mv $@.tmp $@
|
|
|
|
$(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
|
|
sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
|
|
|
|
riscv_junk = \
|
|
$(riscv_gen_srcs) \
|
|
|