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riscv-isa-sim
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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/tests
Tim Newsome d6d23ae847
Only halt on ebreak if a debugger is attached. 		10 years ago
..
debug.c Add some tests that pass and test something. 10 years ago
ebreak.py Only halt on ebreak if a debugger is attached. 10 years ago
ebreak.s Test ebreak without gdb. 10 years ago
gdbserver.py Add --gdb-port 10 years ago
regs.s Do a better job checking CSR functionality. 10 years ago
testlib.py Test ebreak without gdb. 10 years ago