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39 lines
1.2 KiB
39 lines
1.2 KiB
// See LICENSE for license details.
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#ifndef _RISCV_SIMIF_H
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#define _RISCV_SIMIF_H
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#include <map>
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#include "decode.h"
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#include "cfg.h"
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class processor_t;
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class mmu_t;
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// this is the interface to the simulator used by the processors and memory
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class simif_t
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{
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public:
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// should return NULL for MMIO addresses
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virtual char* addr_to_mem(reg_t paddr) = 0;
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virtual bool reservable(reg_t paddr) { return addr_to_mem(paddr); }
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// used for MMIO addresses
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virtual bool mmio_fetch(reg_t paddr, size_t len, uint8_t* bytes) { return mmio_load(paddr, len, bytes); }
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virtual bool mmio_load(reg_t paddr, size_t len, uint8_t* bytes) = 0;
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virtual bool mmio_store(reg_t paddr, size_t len, const uint8_t* bytes) = 0;
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// Callback for processors to let the simulation know they were reset.
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virtual void proc_reset(unsigned id) = 0;
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virtual const cfg_t &get_cfg() const = 0;
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virtual const std::map<size_t, processor_t*>& get_harts() const = 0;
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virtual const char* get_symbol(uint64_t paddr) = 0;
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virtual ~simif_t() = default;
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unsigned nprocs() const { return get_cfg().nprocs(); }
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mmu_t* debug_mmu; // debug port into main memory, for use by debug_module
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};
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#endif
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