riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Spike, a RISC-V ISA Simulator
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
4115 Commits
53 Branches
3 Tags
21 MiB
 
 
 
 
 
 
Tree: 36c40b4853
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '36c40b4853'
${ noResults }
riscv-isa-sim/riscv/insns/wmulu.h

3 lines
79 B
Raw Blame History

require_extension('P');
require_rv32;
WRITE_P_RD_PAIR(zext32(RS1)*zext32(RS2));