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28 lines
537 B
28 lines
537 B
// vsadd.vi vd, vs2 simm5
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VI_CHECK_SSS(false);
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VI_LOOP_BASE
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bool sat = false;
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switch (sew) {
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case e8: {
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VI_PARAMS(e8);
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vd = sat_add<int8_t, uint8_t>(vs2, vsext(simm5, sew), sat);
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break;
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}
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case e16: {
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VI_PARAMS(e16);
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vd = sat_add<int16_t, uint16_t>(vs2, vsext(simm5, sew), sat);
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break;
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}
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case e32: {
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VI_PARAMS(e32);
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vd = sat_add<int32_t, uint32_t>(vs2, vsext(simm5, sew), sat);
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break;
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}
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default: {
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VI_PARAMS(e64);
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vd = sat_add<int64_t, uint64_t>(vs2, vsext(simm5, sew), sat);
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break;
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}
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}
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P_SET_OV(sat);
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VI_LOOP_END
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