Spike, a RISC-V ISA Simulator
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11 lines
222 B

require_rv64;
require_extension('P');
reg_t x = 32 - 1;
reg_t msb = (RS1 >> (32 - 1)) & 1;
for (int i = 0; i < 32 - 1; i++) {
if (msb != ((RS1 >> (32 - i - 2)) & 1)) {
x = i;
break;
}
}
WRITE_RD(sext_xlen(x));