Spike, a RISC-V ISA Simulator

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Tree: 2e816f23cb

arrv-sc-arrv-sc/snippy-tests

confprec

cs250

cycleh

debug_rom

debug_rom_fence

device_flags

dtm_reset_error

dts_parsing

dynamic

eos18-bringup

factor-out-macros

fetch

fix-2296

fix-bf16

force-rtti

fp-encoding

heterogeneous_mc

hwachav4

increase-stack-size

itrigger-etrigger-cleanup

load_reservation_set_size

log-commits-faster

master

mmio-hack

mvp

no_progbuf

no_progbuf2

nolibfdt

optimized-chunk-size

p-ext-0.5.2

plctlab-plct-zce-fix2

plic-clint-endian

plic_uart_v1

priv-1.10

private-l1-caches

pte-info-and-delegation

remove-tests

rivosinc-etrigger_fix_exception_match

rva-profile-support

sanitize

simplify-misaligned

sodor

sparse-mem

speed2

speedup-hacks

static-link

test

tmp

trigger_priority

tweak_debug_rom

whole-archive

zvmm

dummy-tag-for-ci-storage

v1.0.0

v1.1.0

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riscv-isa-sim/spike_main

History

Andrew Waterman 2538c1fb20 Merge pull request #1788 from riscv-software-src/support-larger-addresses Lift restriction on physical-address size		2 years ago
..
spike-log-parser.cc	Move isa property to a field of processor_t, not sim_t	2 years ago
spike.cc	Lift restriction on physical-address size	2 years ago
spike_main.ac	Support setting ISA/subsets with --isa flag	11 years ago
spike_main.mk.in	build: Force inclusion of all symbols from extension.o in spike-main	3 years ago
termios-xspike.cc	Support building from within root directory	12 years ago
xspike.cc	Fix or work around other unused-parameter warnings in ancillary programs	4 years ago