riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Spike, a RISC-V ISA Simulator
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
4041 Commits
53 Branches
3 Tags
19 MiB
 
 
 
 
 
 
Tree: 2e2748b2e0
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '2e2748b2e0'
${ noResults }
riscv-isa-sim/riscv/insns/pasubu_dw.h

4 lines
95 B
Raw Blame History

require_rv32;
P_RD_RS1_RS2_DW_ULOOP(32,32,32, {
p_rd = ((reg_t)p_rs1 - (reg_t)p_rs2) >> 1;
})