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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/hwacha/insns_ut/ut_fmax_h.h

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require_fp;
WRITE_HFRD(isNaNF32UI(HFRS2) || f32_le_quiet(HFRS2,HFRS1) /* && FRS1 not NaN */
? HFRS1 : HFRS2);
set_fp_exceptions;