riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Spike, a RISC-V ISA Simulator
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
336 Commits
54 Branches
3 Tags
19 MiB
 
 
 
 
 
 
Tree: 2cd631a294
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from '2cd631a294'
${ noResults }
riscv-isa-sim/hwacha/insns_ut/ut_fdiv_h.h

4 lines
95 B
Raw Blame History

require_fp;
softfloat_roundingMode = RM;
WRITE_HFRD(f32_div(HFRS1, HFRS2));
set_fp_exceptions;