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riscv-isa-sim
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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/hwacha
Quan Nguyen 9dbe0fac5f
Move half precision instructions, add vfmsv, vfmvv 		12 years ago
..
insns Move half precision instructions, add vfmsv, vfmvv 12 years ago
insns_ut Move half precision instructions, add vfmsv, vfmvv 12 years ago
README revamp hwacha; now runs in physical mode 13 years ago
cvt16.cc Implement "half-baked" half-precision instruction subset for Hwacha 13 years ago
cvt16.h Implement "half-baked" half-precision instruction subset for Hwacha 13 years ago
decode_hwacha.h Merge branch 'confprec' 12 years ago
decode_hwacha_ut.h Move half precision instructions, add vfmsv, vfmvv 12 years ago
encodings_hwacha.h Move half precision instructions, add vfmsv, vfmvv 12 years ago
hwacha.ac revamp hwacha; now runs in physical mode 13 years ago
hwacha.cc Add vsetprec instruction prototype 13 years ago
hwacha.h Fix linking on Darwin 12 years ago
hwacha.mk.in Move half precision instructions, add vfmsv, vfmvv 12 years ago
hwacha_disasm.cc Move half precision instructions, add vfmsv, vfmvv 12 years ago
hwacha_xcpt.h add hwacha exception support 13 years ago
insn_template_hwacha.cc Move half precision instructions, add vfmsv, vfmvv 12 years ago
insn_template_hwacha_ut.cc more hwacha supervisor stuff 13 years ago
opcodes_hwacha.h Move half precision instructions, add vfmsv, vfmvv 12 years ago
opcodes_hwacha_ut.h Move half precision instructions, add vfmsv, vfmvv 12 years ago

README 

This directory contains work in progress on Hwacha, a data-parallel
accelerator.