Spike, a RISC-V ISA Simulator
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Andrew Waterman
2c9a832352
[sim,xcc,pk,opcodes] static rounding modes for FP insns
Now, you can either use the RM in the FSR or specify it in the insn.
(Except for FP->int; no dynamic for that.)
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16 years ago |
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insns
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[sim,xcc,pk,opcodes] static rounding modes for FP insns
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16 years ago |
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applink.cc
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[sim] change applink for tohost/fromhost
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16 years ago |
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applink.h
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[sim] change applink for tohost/fromhost (forgot one file)
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16 years ago |
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common.h
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[sim,xcc] Changed instruction format to RISC-V
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16 years ago |
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decode.h
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[sim,xcc,pk,opcodes] static rounding modes for FP insns
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16 years ago |
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execute.h
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[sim,xcc,pk,opcodes] static rounding modes for FP insns
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16 years ago |
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mmu.h
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[xcc,sim] eliminated vectored traps
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16 years ago |
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processor.cc
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[pk, sim] added FPU emulation support to proxy kernel
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16 years ago |
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processor.h
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[xcc,sim] eliminated vectored traps
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16 years ago |
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riscv-isa-run.cc
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[sim] various fixes to get the sim work with the fesvr
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16 years ago |
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riscv.ac
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[pk, sim] added FPU emulation support to proxy kernel
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16 years ago |
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riscv.mk.in
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[sim] integrated SoftFloat-3 with ISA sim; removed SoftFloat-2b
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16 years ago |
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sim.cc
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[sim] add while to interactive_until
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16 years ago |
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sim.h
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[sim] add while to interactive_until
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16 years ago |
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trap.cc
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Reorganized directory structure
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16 years ago |
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trap.h
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[sim, pk] cleaned up exception vectors and FP exc flags
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16 years ago |
