Spike, a RISC-V ISA Simulator

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Tree: 1ec78cfedd

arromanoff/makefile-type

arrv-sc-arrv-sc/snippy-tests

confprec

cs250

cycleh

debug_rom

debug_rom_fence

device_flags

dtm_reset_error

dts_parsing

dynamic

eos18-bringup

factor-out-macros

fetch

fix-bf16

force-rtti

fp-encoding

heterogeneous_mc

hwachav4

increase-stack-size

itrigger-etrigger-cleanup

load_reservation_set_size

log-commits-faster

master

mmio-hack

mvp

no_progbuf

no_progbuf2

nolibfdt

optimized-chunk-size

p-ext-0.5.2

plctlab-plct-zce-fix2

plic-clint-endian

plic_uart_v1

priv-1.10

private-l1-caches

pte-info-and-delegation

remove-tests

rivosinc-etrigger_fix_exception_match

rva-profile-support

sanitize

simplify-misaligned

sodor

sparse-mem

speed2

speedup-hacks

static-link

test

tmp

trigger_priority

tweak_debug_rom

whole-archive

zvmm

dummy-tag-for-ci-storage

v1.0.0

v1.1.0

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riscv-isa-sim/debug_rom

History

Tim Newsome 1ec78cfedd Fix 2 bugs in Debug ROM: (#52) 1. Debug ROM wasn't actually writing 0xffffffff to the last word in Debug RAM after an exception happened. 2. Fix a race where debug interrupts were cleared before that write would have happened, so a debugger (gdbserver.cc in this case) might get the wrong idea about whether an exception happened or not. Why wasn't this wreaking havoc before?		10 years ago
..
.gitignore	Add gitignore	10 years ago
Makefile	Move debug rom link map to the right place.	10 years ago
debug_rom.S	Fix 2 bugs in Debug ROM: (#52)	10 years ago
debug_rom.h	Fix 2 bugs in Debug ROM: (#52)	10 years ago
link.ld	Move debug rom link map to the right place.	10 years ago