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riscv-isa-sim
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Spike, a RISC-V ISA Simulator
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riscv-isa-sim/hwacha
Yunsup Lee d0a84535eb
correctly trap when SR_EA is disabled 		13 years ago
..
insns clarify vxcptsave/vxctkill semantics 13 years ago
insns_ut can't execute frsr/fssr on ut 13 years ago
README revamp hwacha; now runs in physical mode 13 years ago
decode_hwacha.h implement vxcptsave/vxcptrestore 13 years ago
decode_hwacha_ut.h implement vxcptsave/vxcptrestore 13 years ago
hwacha.ac revamp hwacha; now runs in physical mode 13 years ago
hwacha.cc correctly trap when SR_EA is disabled 13 years ago
hwacha.h clarify vxcptsave/vxctkill semantics 13 years ago
hwacha.mk.in refactor disassembler, and add hwacha disassembler 13 years ago
hwacha_disasm.cc refactor disassembler, and add hwacha disassembler 13 years ago
hwacha_xcpt.h add hwacha exception support 13 years ago
insn_template_hwacha.cc revamp hwacha; now runs in physical mode 13 years ago
insn_template_hwacha_ut.cc more hwacha supervisor stuff 13 years ago
opcodes_hwacha.h add hwacha exception support 13 years ago
opcodes_hwacha_ut.h can't execute frsr/fssr on ut 13 years ago

README 

This directory contains work in progress on Hwacha, a data-parallel
accelerator.