Spike, a RISC-V ISA Simulator

You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

Branch: rivosinc-etrigger_fix_exception_match

arrv-sc-arrv-sc/snippy-tests

confprec

cs250

cycleh

debug_rom

debug_rom_fence

device_flags

dtm_reset_error

dts_parsing

dynamic

eos18-bringup

factor-out-macros

fetch

fix-bf16

force-rtti

fp-encoding

heterogeneous_mc

hwachav4

increase-stack-size

itrigger-etrigger-cleanup

load_reservation_set_size

log-commits-faster

master

mmio-hack

mvp

no_progbuf

no_progbuf2

nolibfdt

p-ext-0.5.2

plctlab-plct-zce-fix2

plic-clint-endian

plic_uart_v1

priv-1.10

private-l1-caches

pte-info-and-delegation

remove-tests

rivosinc-etrigger_fix_exception_match

rva-profile-support

sanitize

simplify-misaligned

sodor

sparse-mem

speed2

speedup-hacks

static-link

test

tmp

trigger_priority

tweak_debug_rom

whole-archive

zvmm

dummy-tag-for-ci-storage

v1.0.0

v1.1.0

Branches Tags

${ item.name }

Create tag ${ searchTerm }

Create branch ${ searchTerm }

from 'rivosinc-etrigger_fix_exception_match'

${ noResults }

riscv-isa-sim/debug_rom

History

Tim Newsome 4d985feb4e DSCRATCH is now called DSCRATCH0 Fixes build.		4 years ago
..
.gitignore	Parameterize debug ROM contents on XLEN	10 years ago
Makefile	Fix debug_rom.S build command error.	4 years ago
debug_rom.S	DSCRATCH is now called DSCRATCH0	4 years ago
debug_rom.h	Writing non-existent CSRs, access FPRs with mstatus.FS=0 (#311)	7 years ago
link.ld	debug: Use a more practical debug ROM	9 years ago