ffe4998fe5
processor_t unfriends gdbserver_t.
10 years ago
f470ee81e1
Correctly read PC on halt.
10 years ago
8d457d5148
Fix store to clear debug interrupt.
10 years ago
d999dfc0d4
Add debug_module bus device.
This should replace the ROM hack I implemented earlier, but for now both
exist together.
Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
10 years ago
191671a201
ROM -> RAM -> ROM, waiting for debug int.
10 years ago
78332ffbaf
Make sure to translate Debug RAM addresses also.
10 years ago
df640b0cac
Jump to the correct (temporary) Debug RAM address.
10 years ago
7facb16039
Clean up how Debug ROM is included.
I'm not thrilled about including a static copy in so many cc files, and
making the compiler throw it out. But without really grokking the
Makefile this is the best it's going to be.
10 years ago
6835847f47
Can jump to and execute Debug ROM.
Connect with gdb, and the core will jump to Debug ROM and start
executing it. Then it crashes when it jumps to 0x400 because Debug RAM
isn't implemented (and doesn't live there anyway, for now).
10 years ago
ddc061f0fb
Check in compiled debug ROM.
Not everybody will have a cross-compiled toolchain set up when they
build spike.
10 years ago
d20be46eb4
When gdb connects, jump to Debug ROM and segfault.
10 years ago
ae566cba20
Add debug rom code.
10 years ago
576d311ad6
Gutting direct-access gdb.
10 years ago
5d1fb6b8c4
Add writing to DCSR, DPC, DSCRATCH.
Make those 3 CSRs writable.
10 years ago
cdf3116b6e
Actually run the ebreak test.
10 years ago
d6d23ae847
Only halt on ebreak if a debugger is attached.
10 years ago
8571c8791a
Test ebreak without gdb.
Currently this test fails.
10 years ago
fce39bd572
Document attaching with gdb.
10 years ago
d1d8863086
Add --gdb-port
It's necessary to be able to run multiple spikes at once on the same
box.
10 years ago
c57bdaa033
Do a better job checking CSR functionality.
10 years ago
bce01a9ed6
Rename gdbserver-smoke.py to gdbserver.py.
It's not really a smoketest anymore.
10 years ago
4efefcf5fe
Test 'info registers all' as well as 'info all-registers'
10 years ago
9f0d9a4032
Minor cleanup.
10 years ago
0cc52e8e5d
Update regnum handling to match gdb CSR changes.
10 years ago
77a51e91f8
Forgot to add this source.
10 years ago
0bf3e0b2bf
Treat warnings as errors.
The code compiles cleanly right now. Let's keep it that way.
10 years ago
daa39a2204
Implement register writes.
10 years ago
0ba84e9c8e
Properly clean up spike.
10 years ago
64f7d791b7
Implement reading of CSRs.
10 years ago
651ad043ce
Add some tests that pass and test something.
10 years ago
824689f929
Flush icache when using swbps and report to gdb.
10 years ago
3fc2f3d543
Add very basic 'make check'.
The existing stuff all assumes you're writing your tests in C++.
10 years ago
b8805d1b15
Make 'make check' not hang forever.
10 years ago
1f0612d593
Software breakpoints seem to work.
10 years ago
0f660bf864
Rewrite GPL'd code from OpenOCD.
10 years ago
6f9a128a44
Looks like single step works.
10 years ago
bd17c7e5a8
Add -H to start halted.
10 years ago
38b8c095df
Implement binary memory write.
Also set the simulation running again when gdb disconnects.
10 years ago
64f57718a8
Now you can halt/continue from gdb.
10 years ago
c76307945e
Register read looks sane now.
10 years ago
d1ba8b5593
gdb can now read spike memory.
The endianness is wrong, but I think it might be that gdb doesn't have
it right. Need to investigate what architecture gdb thinks it's
debugging.
10 years ago
206b89737c
Hack to the point where gdb reads a register.
10 years ago
9f1ea45e41
Listen on a socket for gdb to connect to.
So far it just listens, and gdb times out because it's not getting any
messages back.
Receive packets and verify their checksum.
10 years ago
111434f61a
Allow delegation of device interrupts
10 years ago
065ad6b114
htif: catch proper store exception ( #44 )
The sim's debug_mmu will generate a trap_load_access_fault if the load
fails, not a trap_store_access_fault. This doesn't materially affect
exection, but results in a nicer log message.
10 years ago
8981e57162
Some bugfixes for CSR reading and setting FS for fflags updates ( #43 )
* csrrc[i] and csrrs[i] don't write CSRs if rs/zimm == 0
* Dirty fp state when setting new fp exceptions
* Set FS to dirty for all non-zero fflags writes.
10 years ago
07d2edff33
Merge pull request #42 from csail-csg/master
Removed devicetree.h from riscv.mk.in since it no longer exists
10 years ago
2306679f78
Removed devicetree.h from riscv.mk.in since it no longer exists
10 years ago
9186ae5876
Added missing header files to riscv.mk.in
Merges #40
10 years ago
0d084d5686
Add back IPI support
10 years ago
Tim Newsome
Andrew Waterman
Garret Kelly
Andy Wright