riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4102 Commits
53 Branches
3 Tags
21 MiB
Tree: fce96c0b14
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'fce96c0b14'
${ noResults }
Commit Graph

11 Commits (fce96c0b14fad4d3226206e29db4b680652396c9)

Author SHA1 Message Date
Jerry Zhao fa4079bcba Use relative include paths to support public usage of these headers
4 years ago
Jerry Zhao 9f93b98c87 Rename memif_endianness_t to endianness_t
4 years ago
Jerry Zhao 4d4159e76d Pull memif_endianness_t into cfg.h
4 years ago
Jerry Zhao b265325d19 Remove set_target_endianness | add --big-endian flag
4 years ago
Jerry Zhao cefccba8cf Remove memif_endianness_undecided, change default to little-endian
4 years ago
Jerin Joy f5ec721fa9 Fixed -Wnon-virtual-dtor warnings
4 years ago
Andrew Waterman f8752d8fee Suppress several unused-parameter warnings in fesvr
4 years ago
Iman Hosseini dfd1913679 detects the loading of isa-incompatible (i.e. 32 bit code to 64bit HART) code and emits an error message to help avoid unintentionally loading wrong elf.
4 years ago
Marcus Comstedt 8e3bcb2eef Tag target endian values to help guide conversion code
6 years ago
Marcus Comstedt 8d09d845a7 Implement support for big-endian targets
6 years ago
Andrew Waterman f49618ca9d Add fesvr; only globally install fesvr headers/libs
7 years ago