riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
2859 Commits
54 Branches
3 Tags
19 MiB
Tree: fb57d7ce04
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'fb57d7ce04'
${ noResults }
Commit Graph

2 Commits (fb57d7ce040fbc07197ee76e2afc46cb42cce5e3)

Author SHA1 Message Date
Tim Newsome 5e1bdfc496 Use nproc or hw.ncpu instead of -j4 to build spike.
3 years ago
Tim Newsome 582f4d442e Refactor build-spike out of test-spike.
3 years ago