riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Jerry Zhao	fa4079bcba	Use relative include paths to support public usage of these headers	3 years ago
Jerry Zhao	8c1b434d63	Don't install instruction decode macros	3 years ago
Jerry Zhao	e1919d3b06	Add config.h includes directly to source files instead of relying on header chaining This step is to ensure that removing config.h out of headers will not cause regressions.	3 years ago
Andrew Waterman	3b9a3f17ba	Merge pull request #1183 from riscv-software-src/macosci Add github actions test on macos	3 years ago
Jerry Zhao	3fb390bf56	Add github actions test on macos	3 years ago
Andrew Waterman	0adec00bd2	Merge pull request #1182 from riscv-software-src/fix-1180 Fix build broken by #1170 and #1180	3 years ago
Andrew Waterman	16be7c743f	Merge pull request #1181 from riscv-software-src/better-error-message Print better error message when requesting >1024 harts	3 years ago
Andrew Waterman	520290888b	Fix build broken by #1170 and #1180 It looks like #1170 and #1180 conflict, so they individually pass CI but collectively don't. Trivially fix by #including <vector>.	3 years ago
Andrew Waterman	3030ddd6b8	Merge pull request #1180 from ucb-bar/cleancfg Pull mmu.h out of cfg.h	3 years ago
Andrew Waterman	56c30037ef	Print better error message when requesting >1024 harts The debug module imposes this restriction and was enforcing it with an assertion. But assertions should be used for internal checks only, not for input validation.	3 years ago
Jerry Zhao	9f93b98c87	Rename memif_endianness_t to endianness_t	3 years ago
Jerry Zhao	4d4159e76d	Pull memif_endianness_t into cfg.h	3 years ago
Jerry Zhao	ebc9367677	Add cfg.cc to hold internal implementation of mem_cfg_t	3 years ago
Andrew Waterman	0cb203b0de	Merge pull request #1170 from ucb-bar/decode_macros Split decode.h into public decode.h and internal decode_macros.h	3 years ago
Jerry Zhao	1d6381386c	Split decode.h into public decode.h and private decode_macros.h * decode.h contains constants/typedefs/classes. This should not depend on config.h * decode_macros.h contains internally used macros, and depends on config.h	3 years ago
Andrew Waterman	d00c01d2af	Merge pull request #1175 from riscv-software-src/fix-mac-build Fix build on M1	3 years ago
Andrew Waterman	f1c0a947be	Fix build on M1 https://github.com/riscv-software-src/riscv-isa-sim/pull/1173 introduced a link error on M1. Fix it.	3 years ago
Andrew Waterman	291188f59c	Merge pull request #1169 from ucb-bar/socketif Move boost asio socket interface to socketif_t	3 years ago
Jerry Zhao	68a3039598	Move boost asio socket interface to socketif_t This reduces dependencies on config.h in sim.h	3 years ago
Andrew Waterman	572d5e4409	Merge pull request #1173 from ucb-bar/splitvu Split vectorUnit into separate source/header files	3 years ago
Jerry Zhao	02d4a3f803	Make the processor_t interface independent of configure'd variables (#1174 ) * Make the interface to processor_t static * Move no-commitlog-enabled warning to processor_t This is in case future user calls processor_t->enable_log_commits() without going through sim_t.	3 years ago
Jerry Zhao	18b8c02b25	Pull vector unit into separate source/header	3 years ago
Jerry Zhao	d043952c8b	Pull p/v_ext_macros.h out of decode.h	3 years ago
Jerry Zhao	e5f6307033	Add Emacs lockfiles to .gitignore (#1171 ) Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu> Signed-off-by: Jerry Zhao <jerryz123@berkeley.edu>	3 years ago
Andrew Waterman	921d56ca7a	Merge pull request #1160 from YenHaoChen/pr-textra Implement textra (tdata3) of triggers	3 years ago
Scott Johnson	b2e6e7637e	Move mhselect_compare into mhselect_interpretation	3 years ago
Scott Johnson	ef5609525f	Use interpret_mhselect() to decide textra compare mode	3 years ago
Scott Johnson	88cfdf2972	Interpret mhselect in centralized place And use that for legalize_mhselect(). Not using the second and third fields yet.	3 years ago
YenHaoChen	f94ba5f423	triggers: add mcontext and hcontext CSRs	3 years ago
YenHaoChen	f6f1509ad0	triggers: add scontext CSR	3 years ago
YenHaoChen	8318edfb5f	triggers: checking textra (tdata3); checking ASID and VMID	3 years ago
YenHaoChen	a0fdc2b225	triggers: implement tdata3 CSR fields	3 years ago
YenHaoChen	8ce096c6aa	refactor: add tdata3_csr_t; preparation for CSR textra	3 years ago
YenHaoChen	b035edab78	refactor: remove proc parameter from functions of module_t	3 years ago
Andrew Waterman	adfaef00e5	Merge pull request #1162 from riscv-software-src/sfence SFENCE.W.INVAL and SFENCE.INVAL.IR should check privilege mode	3 years ago
Andrew Waterman	b09a4dc2ae	Merge pull request #1161 from riscv-software-src/snprintf Avoid use of sprintf	3 years ago
Andrew Waterman	9dc874288c	Avoid use of sprintf in disassembler None of these cases are perf-critical. It was easy to change one of them to use std::string, but the others would have required more refactoring. So, simply change them to use snprintf instead.	3 years ago
Andrew Waterman	69bfc02618	Avoid use of sprintf in trap_t	3 years ago
Andrew Waterman	bc16208aa5	SFENCE.INVAL.IR and SFENCE.W.INVAL are illegal in [V]U modes See discussion on https://lists.riscv.org/g/tech-privileged/message/1213	3 years ago
Andrew Waterman	263af1d153	Simplify implementation of SFENCE.W.INVAL For Spike, this instruction merely performs exception checks, just like SFENCE.INVAL.IR. So, implement it in terms of SFENCE.INVAL.IR.	3 years ago
Scott Johnson	27caa02e7d	Merge pull request #1155 from YenHaoChen/pr-h-not-const hypervisor extension does not hardwire misa.H	3 years ago
YenHaoChen	200ee39b7a	clear mevent.VUINH and mevent.VSINH when misa.H is cleared	3 years ago
YenHaoChen	af99d52f25	add macro N_HPMCOUNTERS (29)	3 years ago
YenHaoChen	1a7e9af460	use extension_enabled('H') instead of extension_enabled_const('H') since misa.H is RW The masked_csr_t does not meet the behavior of mevent because the misa.H is not read-only (hardwired). h/t @kwalker27 reported at https://github.com/riscv-software-src/riscv-isa-sim/pull/1154	3 years ago
YenHaoChen	e878eee235	refactor: add custom CSR class, mevent_csr_t The masked_csr_t does not meet the behavior of mevent because the misa.H is not read-only (hardwired). (fix in the next commit) h/t @kwalker27 reported at https://github.com/riscv-software-src/riscv-isa-sim/pull/1154	3 years ago
Andrew Waterman	55c90c6561	Make require_novirt macro an expression, not a statement This improves composability by allowing its use in other expressions.	3 years ago
Andrew Waterman	2d70e7f166	For trap_t::name, return an std::string instead of a C string This is not a performance-critical case, since this method is invoked only when printing the log and when an exception occurs in the target. This works towards eliminating all uses of sprintf. I could have simply switched to snprintf, but this path seems cleaner.	3 years ago
Scott Johnson	120d070680	Merge pull request #1158 from scottj97/trigger-cleanup Minor trigger cleanup	3 years ago
Scott Johnson	49ccab0fcf	Remove unused constructor arg from match_result_t	3 years ago
Scott Johnson	4b792f570d	Remove no-longer-used match_result_t.fire	3 years ago

1 2 3 4 5 ...

2526 Commits (fa4079bcba75e15ff14f756c3eff1281bad679e2) All Branches Search

2526 Commits (fa4079bcba75e15ff14f756c3eff1281bad679e2)

All Branches