Tree: f971129cb6

arrv-sc-arrv-sc/snippy-tests

confprec

cs250

cycleh

debug_rom

debug_rom_fence

device_flags

dtm_reset_error

dts_parsing

dynamic

eos18-bringup

factor-out-macros

fetch

fix-2296

fix-bf16

force-rtti

fp-encoding

heterogeneous_mc

hwachav4

increase-stack-size

itrigger-etrigger-cleanup

load_reservation_set_size

log-commits-faster

master

mmio-hack

mvp

no_progbuf

no_progbuf2

nolibfdt

optimized-chunk-size

p-ext-0.5.2

plctlab-plct-zce-fix2

plic-clint-endian

plic_uart_v1

priv-1.10

private-l1-caches

pte-info-and-delegation

remove-tests

rivosinc-etrigger_fix_exception_match

rva-profile-support

sanitize

simplify-misaligned

sodor

sparse-mem

speed2

speedup-hacks

static-link

test

tmp

trigger_priority

tweak_debug_rom

whole-archive

zvmm

dummy-tag-for-ci-storage

v1.0.0

v1.1.0

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Commit Graph

1 Commits (f971129cb6f6f097f47b74eb3ce9b1872d6d253a)

Author	SHA1	Message	Date
Andrew Waterman	416c8be88c	Support building from within root directory	12 years ago
Andrew Waterman	b06c8e9f26	Implement timer faithfully rdcycle/rdinstret now have single-instruction granularity. Questionable behavior when timer interrupts occurred around the same time as the compare register is written should be fixed.	12 years ago
Andrew Waterman	590417bec9	Factor out the dummy RoCC accelerator	12 years ago
Andrew Waterman	fb3be24671	Eliminate hwacha <-> riscv circular dependence We now split out the spike executable into another subproject, which depends on both rocket and hwacha	12 years ago