Tree: f2aa295a31

arrv-sc-arrv-sc/snippy-tests

binno-spmp_impl

confprec

cs250

cycleh

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dynamic

eos18-bringup

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fix-2296

fix-bf16

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heterogeneous_mc

hwachav4

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itrigger-etrigger-cleanup

load_reservation_set_size

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master

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optimized-chunk-size

p-ext-0.5.2

plctlab-plct-zce-fix2

plic-clint-endian

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priv-1.10

private-l1-caches

pte-info-and-delegation

remove-tests

rivosinc-etrigger_fix_exception_match

rva-profile-support

sanitize

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sparse-mem

speed2

speedup-hacks

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Commit Graph

4047 Commits (f2aa295a31f6d0de376e807b2dfab5a62418c8dc)

 

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Author	SHA1	Message	Date
YenHaoChen	fa3fa7397f	AIA: Add mvip CSR, where mvip.SEIP, (sometimes) mvip.STIP, and mvip.SSIP are aliases of the bits in mip When mvien is read-only 0, mvip.SEIP and mvip.SSIP are aliases of mip.SEIP and mip.SSIP. Accessing mvip.SEIP and mvip.SSIP reads from and writes to mip.SEIP and mip.SSIP. Accessing mvip.STIP reads from and writes to mip.STIP if menvcfg.STCE=1; otherwise, mvip.STIP is read-only 0.	2 years ago
YenHaoChen	4484d17bd2	AIA: Add read-only 0 mvien CSR (minimal required implementation)	2 years ago
YenHaoChen	9e56a3cb5f	AIA: Add mtopi CSR All bytes of the machine-level iprio array are read-only 0s, and mtopi.IPRIO is always 1 whenever mtopi is not 0.	2 years ago
YenHaoChen	c3f60c99f2	AIA: Add read-only 0 iprio array for machine level	2 years ago
YenHaoChen	d4abc9a71b	AIA: Enable Smcsrind/Sscsrind if supporting Smaia/Ssaia Smaia/Ssaia allocates indirect CSRs 0x30~0x3f for major interrupt priorities and 0x70~0xff for external interrupts (only with an IMSIC).	2 years ago
YenHaoChen	003ced8e99	AIA: Add RV32-only mieh, miph, and midelegh CSRs Existing CSRs mie, mip, and mideleg are widended to 64 bits to support a total of 64 interrupt causes.	2 years ago
YenHaoChen	93a5de6ede	AIA: refactor: Use a new variable, selected_interrupt, for better readability	2 years ago
YenHaoChen	84adcb9326	AIA: refactor: Modulize interrupt selection by default_priority	2 years ago
YenHaoChen	8050278445	AIA: Add isa=..._smaia_ssaia_... option	2 years ago
Tianrui Wei	d6d0804e75	chore: add more decoding support The original decoder in spike doesn't support extracting fields such as funct7 or opcode. This commit adds support for usage in other projects. Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>	1 year ago
Andrew Waterman	75e97c6030	Merge pull request #1987 from riscv-software-src/fix-vssra Fix regression in vssra.vi instruction	1 year ago
Andrew Waterman	d0122b4d63	Standardize on zimm5 rather than (simm5 & 0x1f)	1 year ago
Andrew Waterman	e24b8fc112	Fix regression in vssra.vi instruction The immediate is zero-extended.	1 year ago
Andrew Waterman	b0d7621ff8	Merge pull request #1974 from riscv-software-src/fix_vi_loop_mask Use boolean not bitwise operators in VI_LOOP_MASK macro	1 year ago
Jerry Zhao	9f26f2d767	Use boolean not bitwise operators in VI_LOOP_MASK macro	1 year ago
Andrew Waterman	992e969928	Merge pull request #1967 from mslijepc/mslijepc_20250429_observability-hooks adding observability hooks to mmu	1 year ago
Andrew Waterman	a3f126b3bc	Merge pull request #1972 from riscv-software-src/fix-vlen-32 Fix mask element accesses under VLEN=32	1 year ago
Andrew Waterman	7988172561	Use mask element helpers	1 year ago
Andrew Waterman	be2424bb8c	Add vector mask element helpers	1 year ago
Andrew Waterman	d85cd1081a	Merge pull request #1971 from riscv-software-src/strict-vsetvtype Set vill for vsetvli x0, x0, [different SEW/LMUL ratio]	1 year ago
Andrew Waterman	b5e15e338d	Simplify vsetvli x0, x0, given the error case is handled earlier	1 year ago
Andrew Waterman	81f7c810c8	Set vill for vsetvli x0, x0, [different SEW/LMUL ratio]	1 year ago
Andrew Waterman	84557e3580	Narrow scope of variable	1 year ago
mslijepc	9004e8eace	added observability hooks	1 year ago
Andrew Waterman	77ea9deec2	Merge pull request #1966 from riscv-software-src/tlb-rework Substantially improve uncommon-case memory-system performance	1 year ago
Andrew Waterman	607ba10a93	Significantly up uncommon-case load/store/fetch Mostly matters for misaligned loads and stores and MMIO accesses. Opportunistically skip checking the triggers and some other less-common checks.	1 year ago
Andrew Waterman	8bd26af49e	Factor out instruction fetch from permissions checks	1 year ago
Andrew Waterman	8518255e2d	Allow use of TLB for MMIO accesses	1 year ago
Andrew Waterman	c483949b8e	Allow use of TLB even when memtracers are registered	1 year ago
Andrew Waterman	2d846b1fed	Factor out load/store execution from permissions checks	1 year ago
Andrew Waterman	cf9488b733	Move matched_trigger check off the critical path	1 year ago
Andrew Waterman	59eebf0b47	Avoid memory-allocation anti-pattern on matched_trigger	1 year ago
Andrew Waterman	104c99e363	DRY in instruction fetch; eliminate fetch_temp	1 year ago
Andrew Waterman	18baf4c75e	DRY in mmu_t load/store	1 year ago
Andrew Waterman	92e4f02112	Move commit logging check off the critical path Suppress TLB refill when commit logging is enabled to facilitate this strategy.	1 year ago
Andrew Waterman	52517f7719	Separate ITLB/LTLB/STLB into separate structures This is a performance enhancement, because it prevents some pathological conflict cases (e.g. aligned memcpy), but it also cleans up some aspects of the code (e.g. ITLB refills don't interact with the DTLB).	1 year ago
Andrew Waterman	840e9ba026	Remove unused code in mmu.h	1 year ago
Andrew Waterman	734bd97e91	Fix UB in TLB, making Spike valgrind-safe Avoid accessing pointers to outside of the ultimately referenced object.	1 year ago
Andrew Waterman	597a897e5c	Make mmu_t::fetch_temp an entire page in size Needed for valgrind safety, coupled with next commit.	1 year ago
Andrew Waterman	488e07d75d	Merge pull request #1965 from mmhus/mmhus/smc_deleg Implement Ssccfg & Smcdeleg for spike	1 year ago
Muhammad Moiz Hussain	4764d3c029	Implement Ssccfg & Smcdeleg for spike Signed-off-by: muhammad.moiz.hussain@semidynamics.com	1 year ago
Andrew Waterman	5ef9a61f5f	Merge pull request #1942 from trdthg/svade Add Svadu/Svade Support	1 year ago
Mingzhu Yan	4d3920b262	Add Svade extension Support Spike always supports the Svade extension, this is required by the RVA and RVB profiles	1 year ago
Andrew Waterman	842b700764	Merge pull request #1963 from riscv-software-src/wextra Make compilation with -Wextra -Wall -Werror work	1 year ago
Andrew Waterman	7e80f118e8	Enable many more warnings in CI	1 year ago
Andrew Waterman	143c52fd0d	Do warn about unused variables in regular build	1 year ago
Andrew Waterman	19a6ba33de	Fix the remaining few warnings that Clang catches	1 year ago
Andrew Waterman	ea17df2db5	Suppress unused-argument warnings (-Wextra)	1 year ago
Andrew Waterman	5fb354dce8	Suppress sign-comparison warnings in libfdt/softfloat (-Wextra)	1 year ago
Andrew Waterman	417b778955	Suppress always-true comparison warnings (-Wextra)	1 year ago