riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Chih-Min Chao	f2aa295a31	rvp: replace __int128 with int128_t/uint128_t and guard p-ext by HAVE_INT128 Replace bare __int128 / unsigned __int128 in psshar_dhs.h and psshar_dws.h with the int128_t / uint128_t typedefs from fesvr/byteorder.h, and guard the entire riscv_insn_ext_p list in riscv.mk.in with $(if $(HAVE_INT128),...) matching the existing pattern for the V extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	1 month ago
Chih-Min Chao	91a0debd84	rvp: add missing vxsat CSR writes for 70 saturating instructions Per the P-extension spec, any instruction that performs saturation must set the vxsat CSR to 1 when the result is clamped. 70 instructions were missing this write, addressed here in two ways: 1. Convert P_SAT, P_USAT, and P_USAT_FULL macros from pure expression macros to GCC statement expressions that detect when saturation occurs and write P.VU.vxsat. This automatically fixes ~42 instructions that use these macros (nclip/nclipi/nclipr/nclipri families, psati, psslai, pssh1sadd, pusati, sati, usati, ssh1sadd, sslai, and their packed/double-wide variants). 2. Add explicit vxsat writes to 22 instructions with inline saturation logic that bypasses the macros: - mulq/mulqr/pmulq/pmulqr: set vxsat on INT_MIN * INT_MIN overflow - psas/pssa cross variants: set vxsat from sat_add/sat_sub sat flag - pssha/psshar DW variants: set vxsat from ov overflow flag - pssha/psshar/ssha/sshar: set vxsat in sshamt >= BIT overflow path - pusati_dh/pusati_dw: set vxsat on unsigned range clamping Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	1 month ago
Chih-Min Chao	9983d2049f	rvp: add disassembler Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 months ago
Chih-Min Chao	7a42a63eca	rvp: new instructions from 0.20 The complete set of instructions added for RV32 are: PSSHL.HS SSHL PSSHL.DHS PSSHL.DWS PSSHLR.HS SSHLR PSSHLR.DHS PSSHLR.DWS And for RV64: PSSHL.HS PSSHL.WS SHL PNCLIPP.B PNCLIPP.H PNCLIPP.W PSSHLR.HS PSSHLR.WS SHLR PNCLIPUP.B PNCLIPUP.H PNCLIPUP.W reference: https://www.jhauser.us/RISCV/ext-P/RVP-instrEncodings-020.pdf https://www.jhauser.us/RISCV/ext-P/RVP-baseInstrs-Sail-020.txt Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	2 months ago
Jason	d4a87e9caa	rvp: add packed instructions for rv64 - part2 Add the following categories * packed zip and unzip instructions * packed basic arithmetic and data-move * packed multiply instructions (_w suffix only) * packed accumulate instructions (_w suffix * packed multiply-add instructions (_w/_h suffix * packed sati/usati/srari for rv64 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	4 months ago
Jason	71b7473b5f	rvp: add packed instructions for rv64 - part1 Add the following categories * RD-only element-wise instructions (_w suffix * packed add/sub instructions (_w suffix only) * packed cross instructions (_wx suffix only) * packed accumulation instructions (_ws suffix * packed sign-extend and saturating instructions * packed shift instructions (_w/_ws suffix and * packed compare instructions (_w suffix only) * packed pack instructions (_h/_w suffix only) * rev_rv32/rev/rev16	4 months ago
Jason	2e2748b2e0	rvp: add packed instructions for rv32 - part2 Add the following instructions to rv32 * packed add/sub register-pair instructions * packed cross register-pair instructions * packed absolute register-pair instructions * packed accumulation register-pair instructions * packed sign-extend and saturating * packed shift register-pair instructions * packed compare register-pair instructions * packed pack register-pair instructions * packed zip register-pair instructions * packed narrowing shift and clip register-pair * packed multiply register-pair instructions * packed accumulate register-pair instructions * packed multiply-add register-pair instructions	4 months ago
Jason	e4ad4513c7	rvp: add packed instructions for rv32 - part1 add the following categories * packed add/sub/pli instructions * packed cross instructions * packed absolute instructions * packed accumulation instructions * packed sign-extend and saturating instructions * packed shift instructions * packed compare instructions * packed pack instructions * packed basic arithmetic and data-move * packed multiply instructions * packed accumulate instructions * packed multiply-add instructions * RD-only element-wise register-pair	4 months ago
Chih-Min Chao	5b910fd88f	rvp: add opcode Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	2 months ago
Jason	028a698550	rvp: disasm: add simd and register-pair instruction support	4 months ago
Andrew Waterman	770ce31f75	Merge pull request #2275 from nibrunieAtSi5/fixing-invalid-bdot [#2273][bulknormdot] fixing spurious invalid flag in bulk_norm_dot_no_mult	4 weeks ago
Andrew Waterman	aa9dd6aeda	Merge pull request #2278 from riscv-software-src/reduce-virtual-calls-chunk refactor: remove excessive chunk_max_size calls	4 weeks ago
Alexander Romanov	f369386d5a	refactor: remove excessive chunk_max_size calls These calls are virtual and cause notable overhead	4 weeks ago
Nicolas Brunie	41c31ce427	[#2273 ][bulknormdot] fixing spurious invalid flag in bulk_norm_dot_no_mult Bulk normalized dot product is expected to raise the invalid flag if two products with infinite values and opposite signs are added. Spike function failed to consider the second operand of a product when determining whether the product had infinite value or not, and missed the exclusion of NaN and zero from this case. The zero case is quiet, because it happens for inf * zero which is expected to raise the invalid flag. The qNaN case is not quiet and can cause the apparition of a spurious invalid flag when none were expected.	1 month ago
Andrew Waterman	434570f5a6	Merge pull request #2266 from riscv-software-src/zama16b Implement Zama16b extension	1 month ago
Andrew Waterman	f05baff9f4	Remove unused UNUSED	1 month ago
Andrew Waterman	4172e1a2cc	Implement Zama16b extension	1 month ago
Andrew Waterman	5ea492ac8d	Check triggers for store_slow_path with !actually_store Fixes #2262	1 month ago
Andrew Waterman	79ac5e9368	Correctly check for misalignment on SC/AMO	1 month ago
Andrew Waterman	0d05926e3e	Convert ssamoswap load traps to store traps The difference can manifest when checking triggers.	1 month ago
Andrew Waterman	2219879651	Use underscore to indicate unused tuple field	1 month ago
Andrew Waterman	a515bc5205	Remove extraneous comment	1 month ago
Andrew Waterman	0ad45926ac	Merge pull request #2265 from bwv846/mop_rr_7 Fix duplicate addition of mop_rr_7	1 month ago
Hasmet Akgun	80a1c934d4	Fix duplicate addition of mop_rr_7	1 month ago
Andrew Waterman	5eeeb91efa	Merge pull request #2263 from CircuitSutra/fix_dts_compile_api_hang Fixed dtc_compile API hangs as child process waits to perform "exit()" instead of "_exit()".	1 month ago
cst-saswatm	276be7383b	updated child process exit to _exit	1 month ago
Andrew Waterman	a6fb7578c9	Merge pull request #2261 from riscv-software-src/fix-bulk-norm Bulk normalization granularity is based on VLMAX, not vl	1 month ago
Andrew Waterman	108cf836cb	Bulk normalization granularity is based on VLMAX, not vl	1 month ago
Andrew Waterman	170f398cd4	Merge pull request #2251 from hirooih/make-the-executable-path-relative-from-spike make the executable path relative from spike	1 month ago
Andrew Waterman	509bec19b0	Merge pull request #2253 from 5265325/feat/zvzip Add Zvzip extension.	2 months ago
Zhibo Hong	848474582d	Add Zvzip extension.	2 months ago
Andrew Waterman	204b88deda	Merge pull request #2255 from binno/rvv_crypto_fix disasm: Do not imply Zvbb from RVV crypto groups (#146)	2 months ago
Binno Shen	cd58db2ba7	Merge branch 'master' into rvv_crypto_fix	2 months ago
Andrew Waterman	e6b1a9df4e	Merge pull request #2254 from 5265325/feat/svvptc Add Svvptc extension.	2 months ago
Michelle Wu	e06eae1039	disasm: Do not imply Zvbb from RVV crypto groups (#146 ) Remove EXT_ZVBB enablement from Zvkn, Zvknc, Zvkng, Zvks, Zvksc, Zvksg • Zvkn = Zvkned + Zvknhb + Zvkb + Zvkt • Zvknc = Zvkn + Zvbc • Zvkng = Zvkn + Zvkg • Zvks = Zvksed + Zvksh + Zvkb + Zvkt • Zvksc = Zvks + Zvbc • Zvksg = Zvks + Zvkg	2 months ago
Zhibo Hong	38f162ccd0	Add Svvptc extension.	2 months ago
Hiroo HAYASHI	b386d87922	make the executable path relative from spike If the relative path cannot be found, use the current PREFIX. Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>	2 months ago
Andrew Waterman	76ced61f54	Merge pull request #2209 from 5265325/feat/zvabd Add Zvabd extension.	2 months ago
Zhibo Hong	3bfe3ce5ee	Add Zvabd extension.	6 months ago
Andrew Waterman	5968cbe53e	Merge pull request #2242 from Steven-Li-Xiaogang/master fix M-mode access scountovf according to Sscofpmf Version V1.0	2 months ago
steven	926d1c01d8	fix M-mode access scountovf according to Sscofpmf Version V1.0	2 months ago
Andrew Waterman	591cff1610	Merge pull request #2207 from riscv-software-src/fix-2206 Only set mstatus.VS for legal vector instructions	3 months ago
Andrew Waterman	a437348306	Retire dirty_vs_state macro Reduce chance that it gets misused again in the future.	3 months ago
Andrew Waterman	a665eb0337	Don't write vstart in set_vl All callers (the vector_unit constructor and the vsetvl instructions) already initialize or otherwise zero vstart.	3 months ago
Andrew Waterman	ea29ce276c	Make sure VS is set on fault-only-first loads in all cases We weren't setting it in the case that an exception was detected on element 0, which is technically OK since no state changed, but is inconsistent with how we handle regular vector loads.	3 months ago
Andrew Waterman	17682e173d	Make all vector ALU instructions invoke VECTOR_END, dirtying VS dirty_vs_state is therefore no longer needed at the top in require_vector. Furthermore, the vstart write in VECTOR_END dirties VS, so dirty_vs_state is not needed.	4 months ago
Andrew Waterman	e8e3a747d5	Dramatically simplify whole-register loads/stores This makes the vstart/VS handling identical to regular vector loads/stores	3 months ago
Andrew Waterman	ae1531c207	Merge pull request #2239 from riscv-software-src/fix-2238 Make minstretcfg/mcyclecfg privilege bits read-only zero as appropriate	3 months ago
Andrew Waterman	114be91bbe	Remove incorrect use of static variable It prevents modeling mixed RV32/RV64 systems.	3 months ago
Andrew Waterman	0714f0f588	Simplify masking of mnstatus bits when H is toggled	3 months ago

1 2 3 4 5 ...

4047 Commits (f2aa295a31f6d0de376e807b2dfab5a62418c8dc) All Branches Search

4047 Commits (f2aa295a31f6d0de376e807b2dfab5a62418c8dc)

All Branches