Previously any access to the PMPADDRx CSRs when no PMP regions were
configured would result in an illegal instruction trap, whilst
PMPCFGx registers would act as WARL, ignoring writes and reading as 0.
This unifies the behaviour so both PMPADDRx and PMPCFGx CSRs produce an
illegal instruction trap when accessed when no PMP regions are
configured.
change the extention check for F/D/Zfh instructions
modify the F/D/Zfh instructions to read X regs when enable Zfinx
Co-authored-by: wangmeng <shusheng8495@hotmail.com>
Before this commit Spike was requiring S mode privilege even without
S mode implemented. This commit fixes it.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Pursuant to https://github.com/riscv-software-src/riscv-isa-sim/issues/668 and https://github.com/riscv-software-src/riscv-isa-sim/issues/194, allowing for additional exceptions to be delegated from M-mode.
It is implementation-defined whether these bits are defined or are read-only-zero.
QEMU implements the added bits (Fetch/Load/StoreAMO access, Load/StoreAMO misalignment, and illegal instruction). (f6cce6bcb2/target/riscv/csr.c (L813))
ECALL_FROM_M is not implemented here because it would have no effect, although QEMU does implement it.
This allows Spike to emulate QEMU and other systems which allow for the delegation of such exceptions.
Signed-off-by: Brendan Sweeney <mehnadnerd@gmail.com>
Normally, csrs will reuse the checks in verify_permissions of its base csr type
This modification will not cause any functional change, just reuse the check
in csr_t class to check whether it writes to read-only csr instead of checking
writes to counter_proxy_csr_t by itself.
It was accessing memory using the current privilege mode instead of
the expected guest privilege.
Once #872 is fixed, I suspect we can greatly simplify this.
They were accessing memory using the current privilege mode instead of
the expected guest privilege.
Once #872 is fixed, I suspect we can greatly simplify this.
- If U-mode is not supported, then registers menvcfg and menvcfgh do not exist
- Since H extension requires S-mode, and S mode can not exsit without U-mode,
so senvcfg, henvcfg/henvcfgh also do not exist if U-mode is not supported
the default target endian is always little endian:
- mmu::is_target_big_endian() return false
- sim_t::get_target_endianness() return memif_endianness_little
when RISCV_ENABLE_DUAL_ENDIAN macro is undefined
Rupert Swarbrick
Andrew Waterman
Scott Johnson
yangcheng
ksco
Greg Chadwick
Weiwei Li
liweiwei90
i2h2
Canberk Topal
Tim Newsome
ChunPing Chung
Brendan Sweeney