riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Marcus Comstedt	e4419aa79a	Fix new ELF checks on big endian hosts (#567 ) The new macros IS_ELF_... introduced in `80b5b2f5` were not endian safe.	6 years ago
Andrew Waterman	72e5cabe6e	Raise correct exception for counters when V=1 Resolves #566	6 years ago
Andrew Waterman	f1c24eff54	Merge pull request #565 from chihminchao/rvv-fix-2020-10-06 Rvv fix 2020 10 06	6 years ago
Chih-Min Chao	681fbac9ab	rvv: remove elen >= max(xlen, flen) check The original constraint is for baseline u-arch but could be more flexsible Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	f37ebaca77	rvv: commitlog: get hartid directly To avoid handling inconsistent csr status when running with reference design Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	77030fe8c2	rvv: vamo needs to keep exception index in vstart Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	4bacf96d6c	rvv: sstatus.SD needs to include vs dirty state (#563 ) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Abhinay Kayastha	057a601439	Update SATP and HGATP mask usage to make it clearer (#564 )	6 years ago
Andrew Waterman	b1d370cb41	Fix Mac OS build	6 years ago
Andrew Waterman	8966775ab4	It should never be possible to select MPP=2 This completes the fix in `8d860c1906` to cover the hypervisor extension case as well. Fixes #557	6 years ago
Chih-Min Chao	ef3ea15aba	decode: only return meaningful bits for insn_t (#561 ) The original insn_t has the upper part with extended signed bit when the instruction is fetched from mmu_t::refill_icache. It makes the tval of illegal instruction exception wrong. ref: As the spec 3.1.17 says, after an illegal instruction trap, mtval will contain the shortest of: 1. the actual faulting instruction 2. the first ILEN bits of the faulting instruction 3. the first XLEN bits of the faulting instruction The value loaded into mtval is right-justified and all unused upper bits are cleared to zero. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Abhinay Kayastha	0748aa4b46	Partially revert removal of .pc.in files; add disasm.pc.in	6 years ago
sthiruva	4baf970f1b	Adding symbol lookup when --enable-commitlog is enabled (#558 ) * Adding symbol lookup when --enable-commitlog is enabled * Removed the #ifdef RISCV_ENABLE_COMMITLOG for all get_symbol related function Only retained the in processor.cc where it is called. Co-authored-by: Shajid Thiruvathodi <sthiruva@valtrix.in>	6 years ago
sthiruva	e7cdd75724	Add core id to lines generated by --log-commits (#556 ) * Add core id to lines generated by --log-commits * Fixing the format specifier for cpuid in log-commits Co-authored-by: Shajid Thiruvathodi <sthiruva@valtrix.in>	6 years ago
Chih-Min Chao	9d1fb489c2	pmp: fix local scope issue (#552 ) There is an global 'res' in function and local 'res' in pmpcfg loop. This makes the 'ret' macro use the local res but what we want is to pass local result to global 'res' Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Andrew Waterman	9ac9ff2c6e	correctly respect mstatus.TW and hstatus.VTW	6 years ago
Andrew Waterman	14ad0d98e4	Correctly respect mstatus.TSR It never has effect when V=1.	6 years ago
Andrew Waterman	c6a5585849	Correctly respect mstatus.TVM It never has effect when V=1. HFENCE.GVMA and the hgatp CSR must respect it (when V=0).	6 years ago
Andrew Waterman	348fc0c970	Fix priority of virtual vs. illegal instruction exceptions for HFENCE	6 years ago
Andrew Waterman	77024fa1d1	Fix priority of virtual vs. illegal instruction exceptions for HLV/HSV Resolves #551	6 years ago
Andrew Waterman	43003ea3ed	Merge pull request #550 from chihminchao/rvv-pre-1.0-2020-09-22 Rvv pre 1.0 2020 09 22	6 years ago
Chih-Min Chao	0c60f1008b	rvv: commitlog: add peek parameter to get_csr commitlog needs to read all affected csrs but some of them may violate the permisson. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	b8832af2d9	rvv: fix vfncvt/vfwcvt type checking for each case, use explicit type checking Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Andrew Waterman	648e16e778	Add basic continuous-integration flow	6 years ago
Andrew Waterman	4672cf245c	Only install pkg-config files for libraries that are installed Resolves #549	6 years ago
Andrew Waterman	59d450e586	Separate build of spike and spike-dasm	6 years ago
Andrew Waterman	b1dc3826d0	Don't error out if dlopen isn't available	6 years ago
Andrew Waterman	ac46e18f82	Raise virtual-instruction traps correctly for WFI/SRET/SFENCE	6 years ago
Andrew Waterman	fbb5a7620f	Fix polarity of hstatus.HU field	6 years ago
Andrew Waterman	d6ac560a1c	Don't throw virtual instruction exceptions for unimplemented CSRs	6 years ago
Han-Kuan Chen	3e7cba464d	rvv: fix int type is not enough to do shift (#544 ) int can only represent 32 bit in lp64 model when sew is greater than 32, the behavior is undefined	6 years ago
Andrew Waterman	a3376ff9af	Populate tval registers on illegal-/virtual-instruction traps	6 years ago
Andrew Waterman	8957a8efec	No need to catch illegal CSRs in set_csr get_csr is always called first (and this assumption is pervasively relied upon), so the checks in set_csr are redundant. FYI @avpatel	6 years ago
Abhinay Kayastha	58f23e111f	Add MIP_MEIP to all_ints (#543 )	6 years ago
Andrew Waterman	ecc87c4ce3	Merge pull request #542 from chihminchao/rvv-fix-2020-09-08 Rvv fix 2020 09 08	6 years ago
Chih-Min Chao	57fbf0eeb1	rvv: disasm: separate vvm and vv Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	f398f0af9b	rvv: disasm: fix vamoadd name Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Anup Patel	3101b47288	Fix MIDELEG and MEDELEG emulation when H-extension is available (#537 ) This patch does two fixes when H-extension is available: 1. The MEDELEG should allow delegating VIRTUAL_SUPERVISOR_ECALL instead of SUPERVISOR_ECALL. This was broken after commit `7775c6fb7c`. 2. The forced bits in MIDELEG should be cleared when 'H' bit is cleared in MISA CSR. Signed-off-by: Anup Patel <anup.patel@wdc.com>	6 years ago
Andrew Waterman	f974ce1c6d	Merge pull request #535 from chihminchao/rvv-pre-1.0-2020-08-27 Rvv pre 1.0 2020 08 27	6 years ago
Chih-Min Chao	989f8772f3	rvv: reading vcsr needs to enable mstatus.vs Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	526b9abb7c	rvv: disasm: fix amo sub-opcode Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	52b3eb9380	rvv: disasm: fix whole load Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	6f7b46f71f	rvv: relax checking for vs1 vs1 is sub-op Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	69fcd8d2fe	rvv: trigger exp for illegal ncvt/wcvt eew Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	fa23a1cc1d	rvv: check invalid frm for floating operations Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	c9da294332	rvv: add reciprocal instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	eceda60356	softfloat: add reciprocal api Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	e11db4e6c9	rf: remove bit extraction from processor.h Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Chih-Min Chao	bfc2bead78	rvv: remove quad instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	6 years ago
Tim Newsome	5f76a0d1fa	Fix debug tests failing with impebreak enabled. (#530 ) Introduced in #527.	6 years ago

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1397 Commits (e4419aa79a3c999e85610616d6e85847b08f7e19) All Branches Search

1397 Commits (e4419aa79a3c999e85610616d6e85847b08f7e19)

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