riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Andrew Waterman	e2eb763332	Add ci-tests/.gitignore	10 months ago
Andrew Waterman	4a429d146d	Install cross compiler package	10 months ago
Andrew Waterman	ffcc3e69a7	Actually use -Werror in CI again	10 months ago
Andrew Waterman	e69c5376a5	Suppress warning for unused write() result	10 months ago
Andrew Waterman	9ea67d0ca8	Add UNUSED to suppress warning	10 months ago
Andrew Waterman	eb90f5aa75	Add default destructor to suppress warning	10 months ago
Andrew Waterman	837fcf7c15	Avoid VLAs	10 months ago
Andrew Waterman	aee4555eea	Merge pull request #2092 from riscv-software-src/zvfqbdot8f Implement Zvfqbdot8f and Zvfqldot8f	10 months ago
Andrew Waterman	3232ce1b76	Implement Zvflqdot8f	10 months ago
Andrew Waterman	e3dc14a878	Implement Zvfbqdot8f	10 months ago
Andrew Waterman	a07e44071f	Use bulk normalization algorithm for Zvfqbdot8f	10 months ago
Andrew Waterman	3b066d68fe	Merge pull request #2089 from chihminchao/fix-mseccfg-rv32 csr: fix mseccfg for rv32	10 months ago
Andrew Waterman	b3b7ed4c36	Merge pull request #2091 from aap-sc/aap-sc/leakage_fix Get rid of leaking pointers in examples for custom extension	10 months ago
Parshintsev Anatoly	a191144b7a	Get rid of leaking pointers in examples for custom extention Building of spike-based simulator with memory sanitizer reports leaking pointers if custom extension are used. This is because existing facilities do not have a proper destructor procedure, so the objects representing custom extentions are leaked. This commit implements quick-and-dirty fix for the problem.	10 months ago
Chih-Min Chao	180c10fe42	csr: fix mseccfg for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	10 months ago
Andrew Waterman	bfe100fbd3	Merge pull request #2088 from ved-rivos/issue_2078 PTE store in s2xlate should use the trap_type instead of type	11 months ago
Ved Shanbhogue	cfd4930cb6	PTE store in s2xlate should use the trap_type instead of type	11 months ago
Andrew Waterman	f51df5d395	Merge pull request #2077 from riscv-software-src/fix-2076 Prevent div-by-0 when executing Zvbdot instructions with VLEN=0	11 months ago
Andrew Waterman	18bcac3d94	Prevent div-by-0 when executing Zvbdot instructions with VLEN=0 Fixes #2076	11 months ago
Andrew Waterman	545712a6f7	Merge pull request #2074 from riscv-software-src/fix-2073 Allow DEBUG_START to be nonzero again	11 months ago
Andrew Waterman	e80b890ebf	Suppress -Wtype-limits warning	11 months ago
Andrew Waterman	3d85f9af29	Merge pull request #2072 from ved-rivos/issue_2063 Clear SDT in the temporary state variable	11 months ago
Ved Shanbhogue	743732c3e6	Clear SDT in the temporary state variable	11 months ago
Andrew Waterman	d3be9a4d9d	Merge pull request #2069 from riscv-software-src/fix-zve Relax VLEN/ELEN checking	11 months ago
Andrew Waterman	1d56b556b5	Relax VLEN/ELEN checking We should allow ISA strings like rv64gc_zve32f. Per the spec, the various Zve extensions imply a minimum VLEN, so rv64gc_zve32f is unambiguously equivalent to rv64gc_zve32f_zvl32b. Similarly, rv64gc_zve64x, rv64gc_zve64x_zvl64b, and rv64gc_zve64x_zvl32b are all unambiguously equivalent.	11 months ago
Andrew Waterman	faeae4eada	VLEN is unitless	11 months ago
Andrew Waterman	acac77d59d	No tabs	11 months ago
Andrew Waterman	c3ec317126	Merge pull request #2066 from riscv-software-src/quiet-ci Quiet the CI logs	11 months ago
Andrew Waterman	7e389e824f	Quiet the CI logs Send instruction traces to /dev/null to make the CI logs readable.	11 months ago
Andrew Waterman	19409bdfac	Merge pull request #2065 from riscv-software-src/ldot Add Zvldot extension support	11 months ago
Andrew Waterman	dcef3e5881	Merge pull request #2054 from nadime15/update_vlen_elen Add VLEN >= ELEN validation check	11 months ago
Andrew Waterman	717a6e275c	Add Zvldot extension support	11 months ago
Andrew Waterman	cfc472e83b	Use f32_add_bulknorm_odd for vfwbdot	11 months ago
Andrew Waterman	cf7d57ef74	Add f32_add_bulknorm_odd routine Used by Zvldot/Zvbdot	11 months ago
Andrew Waterman	9c190a07c6	Merge pull request #2058 from nadime15/fix-zvfbf-dependency-check Fix BFloat16 vector extension dependencies and requirements	11 months ago
Nadime Barhoumi	dcb5f0c784	Remove redundant checks in Zfbfmin and Zvfbfmin validation	11 months ago
Nadime Barhoumi	715c1597ab	Fix BFloat16 vector extension dependencies * Enable EXT_INTERNAL_ZFH_MOVE when either Zfbfmin or Zfhmin is enabled * Change Zvfbfmin to require Zve32f instead of V extension. * Add proper dependency chain for Zvfbfwma requiring both Zvfbfmin and Zfbfmin.	12 months ago
Andrew Waterman	9a46080b52	Merge pull request #2062 from binno/revert_vstopi_change Revert "Don't shift enabled bits of interrupt in vstopi csrs"	11 months ago
Binno	faeecd8d72	Revert "Don't shift enabled bits of interrupt in vstopi csrs" This reverts commit `e515a8fbcd`.	11 months ago
Andrew Waterman	eff659cd43	Merge pull request #2056 from binno/remove_shift_in_vstopi Don't shift enabled bits of interrupt in vstopi csrs	1 year ago
Binno	e515a8fbcd	Don't shift enabled bits of interrupt in vstopi csrs Signed-off-by: Binno <binno.shen@sifive.com>	1 year ago
Nado15	23ad840e4d	Add VLEN < ELEN validation check	1 year ago
Andrew Waterman	1553a2a896	Merge pull request #2053 from riscv-software-src/fix-2052 Support FLI.H for Zfa && Zvfh && !Zfh	1 year ago
Andrew Waterman	d0c345184f	Support FLI.H for Zfa && Zvfh && !Zfh Resolves #2052	1 year ago
Andrew Waterman	e17097aaea	Merge pull request #2051 from riscv-software-src/fix-2050 Fix regression introduced by #2050	1 year ago
Andrew Waterman	d951d9bc6a	Fix regression introduced by #2050 Don't assert SEW=8 for fp16 <> int8 conversions.	1 year ago
Andrew Waterman	5da583ee34	Merge pull request #2050 from riscv-software-src/vfp-refactor Factor out common vector FP prologue	1 year ago
Andrew Waterman	4e4d9f99ee	Factor out rounding-mode validation	1 year ago
Andrew Waterman	3c0db13b52	Factor out common vector FP prologue	1 year ago
Andrew Waterman	2dfd52759b	Merge pull request #2049 from riscv-software-src/vector-cleanup Minor vector-unit cleanup	1 year ago

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3806 Commits (e2eb763332bd1d0f786c775ac2642c1a163aa065) All Branches Search

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