The current spike implementation does not include the ILEN (maximum
instruction length supported by the implementation), which is required
to constrain the value of tval on an illegal instruction exception.
Consider an implementation supporting only an RV64I base instruction
set. The ILEN is 32 bits (spec sec. 1.5), and the MXLEN is 64 bits (spec
sec. 5.1). Under an illegal instruction exception with the instruction
longer than the ILEN, the mtval should contain the first ILEN (32 bits)
of the faulting instruction. However, the current spike implementation
lets the mtval be the instruction's first MXLEN (64 bits).
To fix this bug, this PR masks out the upper bits of the tval and leaves
the first ILEN bits of the faulting instruction. When this PR is being
made, all official instructions are either 16 or 32 bits. So, We hard-
code the ILEN to 32 bits.
Previously any access to the PMPADDRx CSRs when no PMP regions were
configured would result in an illegal instruction trap, whilst
PMPCFGx registers would act as WARL, ignoring writes and reading as 0.
This unifies the behaviour so both PMPADDRx and PMPCFGx CSRs produce an
illegal instruction trap when accessed when no PMP regions are
configured.
change the extention check for F/D/Zfh instructions
modify the F/D/Zfh instructions to read X regs when enable Zfinx
Co-authored-by: wangmeng <shusheng8495@hotmail.com>
Before this commit Spike was requiring S mode privilege even without
S mode implemented. This commit fixes it.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Pursuant to https://github.com/riscv-software-src/riscv-isa-sim/issues/668 and https://github.com/riscv-software-src/riscv-isa-sim/issues/194, allowing for additional exceptions to be delegated from M-mode.
It is implementation-defined whether these bits are defined or are read-only-zero.
QEMU implements the added bits (Fetch/Load/StoreAMO access, Load/StoreAMO misalignment, and illegal instruction). (f6cce6bcb2/target/riscv/csr.c (L813))
ECALL_FROM_M is not implemented here because it would have no effect, although QEMU does implement it.
This allows Spike to emulate QEMU and other systems which allow for the delegation of such exceptions.
Signed-off-by: Brendan Sweeney <mehnadnerd@gmail.com>
Normally, csrs will reuse the checks in verify_permissions of its base csr type
This modification will not cause any functional change, just reuse the check
in csr_t class to check whether it writes to read-only csr instead of checking
writes to counter_proxy_csr_t by itself.
Iman Hosseini
Scott Johnson
Andrew Waterman
Weiwei Li
Kip Walker
Rupert Swarbrick
YenHaoChen
yangcheng
ksco
Greg Chadwick
liweiwei90
i2h2
Canberk Topal
Tim Newsome
ChunPing Chung
Brendan Sweeney