riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Ved Shanbhogue	08bad17b04	add byte width amo instructions	3 years ago
Andrew Waterman	eeef09ebb8	Merge pull request #1489 from nibrunieAtSi5/patch-1 Fixing minor typo in comment Gallois -> Galois	3 years ago
Nicolas Brunie	434138e109	Fixing minor typo Gallois -> Galois Signed-off-by: Nicolas Brunie <82109999+nibrunieAtSi5@users.noreply.github.com>	3 years ago
Andrew Waterman	f6104dd6ca	Merge pull request #1487 from mehnadnerd/zalasr Adding Zalasr support.	3 years ago
brs	37e00ffb6e	Update README on adding new instructions to point out that they need to be added to riscv.mk.in	3 years ago
brs	177ecae365	Update to Zalasr encodings to require the aq/rl bits be set rather than assuming they are	3 years ago
brs	9258b59e67	Spike support for the Zalasr extension	3 years ago
Andrew Waterman	67252b3d7c	Merge pull request #1486 from riscv-software-src/zcmop Add unratified Zcmop extension	3 years ago
Ved Shanbhogue	762ed3f5c8	add zcmop extension instructions	3 years ago
Andrew Waterman	4eb1cceb3d	Revert "tmp" This reverts commit `1de1e81952`.	3 years ago
Andrew Waterman	a2e80e1eba	Merge pull request #1484 from riscv-software-src/zcmop add zcmop extension instructions	3 years ago
Andrew Waterman	1de1e81952	tmp	3 years ago
Andrew Waterman	36b21070c5	Merge pull request #1483 from riscv-software-src/debug_tests workflow: Update riscv-openocd and riscv-tests versions	3 years ago
Tim Newsome	68d4f6faff	workflow: Update riscv-openocd and riscv-tests versions Make sure we test with recent OpenOCD and tests.	3 years ago
Andrew Waterman	6986742686	Merge pull request #1481 from chihminchao/remove-vector-amo Remove vector amo	3 years ago
Chih-Min Chao	e84ef9385c	vamo: remove disassembler Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Chih-Min Chao	9ffcbc3556	vamo: remove related loop macro Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Chih-Min Chao	9705dc3ba8	vamo: remove instruction implementation Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Chih-Min Chao	2e24763045	vamo: remove from building list Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Andrew Waterman	b5d13f3605	Merge pull request #1477 from abejgonzalez/patch-1 Update dtm.h with switch_to_* functions	3 years ago
Abraham Gonzalez	c5eee7426d	Update dtm.h with switch_to_* functions Signed-off-by: Abraham Gonzalez <abe.j.gonza@gmail.com>	3 years ago
Andrew Waterman	d1efcdffff	Merge pull request #1473 from riscv-software-src/unavailable Fix behavior of unavailable harts.	3 years ago
Tim Newsome	77e9aaef19	debug: Abstract commands fail on unavailable harts.	3 years ago
Tim Newsome	7613da4d26	debug: Halted harts can also be unavailable.	3 years ago
Andrew Waterman	847fe5d59a	Merge pull request #1471 from mehnadnerd/patch-1 Change disasm for vset{i}vli with reserved vtypes to display the reserved bits	3 years ago
Brendan Sweeney	cf3f787474	Change disasm for vset{i}vli with reserved vtypes to display the reserved bits Currently there is a bug with the disassembly when vsetivli/vsetvli have invalid vtypes (with reserved bits set). Spike correctly detects this and sets vill, but the disassembler integrated into spike ignores those bits being set and prints the instruction as if they weren't. This makes debugging harder, it looks like an otherwise valid vtype was being rejected and can lead down debugging paths like thinking the vector unit is configured incorrectly. This commit changes the behaviour so that if these reserved bits are set, it prints out the hex value of the vtype. This is understood by the assembler. GCC disassembler prints out the decimal value of the vtype in this case, I think that hex value is clearer but I can change it if desired. Signed-off-by: Brendan Sweeney <brs@eecs.berkeley.edu>	3 years ago
Andrew Waterman	67df25aedc	Merge pull request #1458 from YenHaoChen/pr-multiple-icount Hit multiple icount triggers with different actions	3 years ago
YenHaoChen	9bc80f3d09	triggers: fix: not decrease icount.count on firing other icount with action=debug	3 years ago
YenHaoChen	7b3b2e94ad	triggers: refactor: icount: breakdown detect_icount_match() into detect_icount_fire() and detect_icount_decrement()	3 years ago
Andrew Waterman	eb9a55a519	Merge pull request #1453 from riscv-software-src/attempt-to-fix-mac-ci Attempt to fix Mac OS CI	3 years ago
Andrew Waterman	e3e610050d	Attempt to fix Mac OS CI	3 years ago
Andrew Waterman	d2d9d995a9	Merge branch 'viktoryou-master'	3 years ago
viktoryou	3c8320ecd7	fix condition of executing cbo.inval as a flush operation Signed-off-by: viktoryou <143797577+viktoryou@users.noreply.github.com>	3 years ago
Ved Shanbhogue	fd410c6f6f	report right pseudo-inst for guest PF caused for VS-stage addr trans	3 years ago
Ved Shanbhogue	ae9888e508	check g-stage write perm and set D bit in g-stage pte for vs-stage pte A/D updates	3 years ago
Andrew Waterman	5854ab5218	Merge pull request #1446 from chihminchao/bf16-nanboxed-access fix bf16 nanboxed access	3 years ago
Chih-Min Chao	eff6c60498	bf16: handle invalid Nan-boxed accessing assume 0x0000_0000_0000_7d2d at 0x8000_0000 a0 = 0x8000_0000 fld ft0, 0(a0) <- load 0x0000_0000_0000_7d2d to ft0, it is invalid Nanboxed fcvt.s.bf16 ft1, ft0 <- read bf16 from ft0. it should be 0x7fc0 (bf16 QNaN) but not 0x7e00 (f16 QNaN) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>	3 years ago
Andrew Waterman	db20475248	Merge pull request #1434 from dansmathers/master update model_test.h: set_msw/clear_msw/set_mtimer/clear_mtimer	3 years ago
Andrew Waterman	d1680b75de	Merge pull request #1438 from liuyu81/master fdt: Install header files `fdt.h` and `libfdt_env.h` as needed by `libfdt.h`	3 years ago
Andrew Waterman	3bea946db3	Merge pull request #1439 from MarkLai0317/fix-include-error Include cerrno in fesvr/elfloader.cc	3 years ago
Mark Lai	c6e2b703c5	Include cerrno in fesvr/elfloader.cc It caused compile error "use of undeclared identifier 'errno'" at line 26 and 33. I Add #include <cerrno> in fesvr/elfloader.cc to fix error and compile successfully.	3 years ago
LIU Yu	05c10a06a3	Install header files fdt.h and libfdt_env.h as needed by libfdt.h	3 years ago
Andrew Waterman	5a499ef718	Merge pull request #1436 from ved-rivos/hade_to_adue Rename envcfg.HADE to envcfg.ADUE	3 years ago
Ved Shanbhogue	07c2e2bfcb	rename envcfg.HADE to envcfg.ADUE	3 years ago
Dan Smathers	179951a015	Merge pull request #1 from dansmathers/dansmathers-patch-1 update set_msw/clear_msw/set_mtimer/clear_mtimer	3 years ago
Dan Smathers	de8e0588ac	update set_msw/clear_msw/set_mtimer/clear_mtimer Added ifndef to clint addresses instead of hard-coding Added clear_msw and clear mtimer Tested against Sail/isa-sim with new proposed Smclint/Ssclint arch-tests https://github.com/riscv-non-isa/riscv-arch-test/pull/372 Building a baseline of interrupt tests that changes to SAIL/isa-sim can be tested against when other interrupt extensions are added. Signed-off-by: Dan Smathers <dan.smathers@seagate.com>	3 years ago
Andrew Waterman	ec3c9357ec	Merge pull request #1427 from YenHaoChen/pr-textra-sbytemask triggers: fix textra.sbytemask	3 years ago
Andrew Waterman	c59e80e980	Merge pull request #1381 from rivosinc/smcntrpmf_feature Add Smcntrpmf support	3 years ago
Atul Khare	c927773dd1	Add Smcntrpmf functionality If Smcntrpmf is enabled, mcycle / minstret increment only if counting for the privilege level isn't inhibited in mcyclecfg / minstretcfg.	3 years ago
Atul Khare	62178539f8	Add prv_changed / v_changed fields to state This tracks whether the privilege / virtual mode was changed by the execution of the current instruction.	3 years ago

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3196 Commits (d39cbb3ad27b2de882260c0a22f11a59efebb151) All Branches Search

3196 Commits (d39cbb3ad27b2de882260c0a22f11a59efebb151)

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