564 Commits (d1d8863086c57f04236418f21ef8a7fbfc184b0b)
 

Author SHA1 Message Date
Tim Newsome d1d8863086 Add --gdb-port 11 years ago
Tim Newsome c57bdaa033 Do a better job checking CSR functionality. 11 years ago
Tim Newsome bce01a9ed6 Rename gdbserver-smoke.py to gdbserver.py. 11 years ago
Tim Newsome 4efefcf5fe Test 'info registers all' as well as 'info all-registers' 11 years ago
Tim Newsome 9f0d9a4032 Minor cleanup. 11 years ago
Tim Newsome 0cc52e8e5d Update regnum handling to match gdb CSR changes. 11 years ago
Tim Newsome 77a51e91f8 Forgot to add this source. 11 years ago
Tim Newsome 0bf3e0b2bf Treat warnings as errors. 11 years ago
Tim Newsome daa39a2204 Implement register writes. 11 years ago
Tim Newsome 0ba84e9c8e Properly clean up spike. 11 years ago
Tim Newsome 64f7d791b7 Implement reading of CSRs. 11 years ago
Tim Newsome 651ad043ce Add some tests that pass and test something. 11 years ago
Tim Newsome 824689f929 Flush icache when using swbps and report to gdb. 11 years ago
Tim Newsome 3fc2f3d543 Add very basic 'make check'. 11 years ago
Tim Newsome b8805d1b15 Make 'make check' not hang forever. 11 years ago
Tim Newsome 1f0612d593 Software breakpoints seem to work. 11 years ago
Tim Newsome 0f660bf864 Rewrite GPL'd code from OpenOCD. 11 years ago
Tim Newsome 6f9a128a44 Looks like single step works. 11 years ago
Tim Newsome bd17c7e5a8 Add -H to start halted. 11 years ago
Tim Newsome 38b8c095df Implement binary memory write. 11 years ago
Tim Newsome 64f57718a8 Now you can halt/continue from gdb. 11 years ago
Tim Newsome c76307945e Register read looks sane now. 11 years ago
Tim Newsome d1ba8b5593 gdb can now read spike memory. 11 years ago
Tim Newsome 206b89737c Hack to the point where gdb reads a register. 11 years ago
Tim Newsome 9f1ea45e41 Listen on a socket for gdb to connect to. 11 years ago
Andrew Waterman 111434f61a Allow delegation of device interrupts 10 years ago
Garret Kelly 065ad6b114 htif: catch proper store exception (#44) 10 years ago
Andy Wright 8981e57162 Some bugfixes for CSR reading and setting FS for fflags updates (#43) 10 years ago
Tim Newsome 07d2edff33 Merge pull request #42 from csail-csg/master 10 years ago
acw1251 2306679f78 Removed devicetree.h from riscv.mk.in since it no longer exists 10 years ago
acw1251 9186ae5876 Added missing header files to riscv.mk.in 10 years ago
Andrew Waterman 0d084d5686 Add back IPI support 10 years ago
Andrew Waterman 64fd5f375c Remove MIPI; mip.MSIP bit is read-only 10 years ago
Andrew Waterman 980a0121e0 Remove tohost/fromhost registers 10 years ago
Andrew Waterman c3b19169fb Initialize mtvec to DEFAULT_MTVEC 10 years ago
Andrew Waterman 32e717a3c6 Remove SCRs; add padding after config string 10 years ago
Andrew Waterman b593e6df7a Move much closer to new platform-M memory map 10 years ago
Andrew Waterman 9220fdfe95 Add --dump-config-string flag 10 years ago
Andrew Waterman a9c5b05eca Remove MTIME[CMP]; add RTC device 10 years ago
Andrew Waterman 27e29e69cc Split ERET into URET, SRET, HRET, MRET 10 years ago
Andrew Waterman 7a2a57b8bc Remove non-standard uarch CSRs 10 years ago
Andrew Waterman 10ae74e48a Allow configuration of default ISA with --with-isa 10 years ago
Andrew Waterman 94c7f5adbe Update definition of base field in misa register 11 years ago
Andrew Waterman fa1cb289e7 Fix up interrupt delegation 11 years ago
Andrew Waterman cb3db40b87 Add counter-enable registers 11 years ago
Andrew Waterman e6685ad87a Use RV config string rather than FDT 11 years ago
Andrew Waterman 5618582e2f WIP on priv spec v1.9 11 years ago
Andrew Waterman b4bc2159c2 New definitions of misa/marchid/mvendorid 11 years ago
Andrew Waterman c0c61f09d8 implement PUM functionality 11 years ago
Andrew Waterman 48e4425644 sptbr now a holds a PPN, not an address 11 years ago