riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Jerry Zhao	cefccba8cf	Remove memif_endianness_undecided, change default to little-endian	4 years ago
Andrew Waterman	5a50590f25	Merge pull request #1122 from riscv-software-src/more-mmu-simplification Fix minor MMU bugs; clean up MMU some more	3 years ago
Andrew Waterman	9cf4e82ec2	Merge pull request #1125 from riscv-software-src/cbo-fixes Fix tval reporting for CBOs; constrain cache-block sizes to reasonable values	3 years ago
Andrew Waterman	c10ad3c85a	Use reg_t, not uint64_t, for address-like quantities	3 years ago
Andrew Waterman	6b689208d9	Fix tval reporting for CBOs mmu_t::translate may raise exceptions and so must be called with the original virtual address for tval to be set correctly.	3 years ago
Andrew Waterman	da21648472	Set 16..4096-byte bound on cache-block size 16 B suffices to subsume all aligned accesses (including the Q extension). Spike does not actually rely on this property, but in some real systems, it is impractical to guarantee atomicity across cache lines. 4096 B suffices to prevent cache lines from spanning pages (which would require multiple TLB accesses). This one is a bug fix, since we were not performing multiple TLB accesses in this case.	3 years ago
YenHaoChen	e8340aedc8	move fucntion cto() from processor.h to arith.h Only triggers.cc uses the arithmetic function cto(). Instead of putting the cto() in processor.h, putting it in arith.h with other arithmetic functions, e.g., ctz() and clz(), makes more sense.	3 years ago
Andrew Waterman	b1f2ae41a1	Template-ize stores	3 years ago
Andrew Waterman	d41af9f81c	Template-ize loads	3 years ago
Andrew Waterman	8d40946475	Template-ize AMOs	3 years ago
Andrew Waterman	7b52a249c8	DRY in store-conditional instructions	3 years ago
Andrew Waterman	635985515f	Simplify check_load_reservation Invoking refill_tlb to get the physical address is somewhat baroque, and not even helpful in practice, since successful SCs will fill the TLB anyway.	3 years ago
Andrew Waterman	5cdb39484c	Template-ize hypervisor loads and stores	3 years ago
Andrew Waterman	a09b88d4ab	Remove require_alignment flag from loads The last remaining use was LR, which we can identify through other means.	3 years ago
Andrew Waterman	905db657f5	Fix imprecise exception on LR to MMIO space The old implementation performed the load before checking whether the memory region was valid for LR. So, for LR to MMIO, we would action side effects before raising the exception, which is not precise.	3 years ago
Andrew Waterman	5746722334	Template-ize load_func macro For now, preserve the macro for compatibility with existing uses.	3 years ago
Andrew Waterman	15bad75ecc	Template-ize store_func macro For now, preserve the macro for compatibility with existing uses.	3 years ago
Andrew Waterman	1caaaa5471	No need to require_alignment for the load part of the AMO The earlier call to store_slow_path will catch the misalignment.	3 years ago
Andrew Waterman	24907dfbd1	Remove actually_store and require_alignment parameters from store_func macro These are now only used by AMOs. Since AMOs are relatively uncommon, and since the slow path really isn't slow anymore, send them down the slow path to simplify the common case.	3 years ago
Weiwei Li	2e12d7251e	remove duplicate CMO item in README.md	3 years ago
Weiwei Li	2b7edec863	do memcpy only for actually_store in store_slow_path_intrapage	3 years ago
Weiwei Li	bc9ee3e427	Fix missing sentinel warning in dts.cc when using gnu++17 standard	3 years ago
bluew	228c117855	Fix forced linking when compiling headers	3 years ago
Andrew Waterman	3f1b236707	fix clang build	4 years ago
Jerry Zhao	a82ef28621	Add command to display privilege level in interactive mode	4 years ago
Andrew Waterman	66a307d6aa	Make PLIC/NS16550 coding style more conformant	4 years ago
Andrew Waterman	68aeeb5500	Merge branch 'master' into plic_uart_v1	4 years ago
Jerry Zhao	03be4ae6c7	Add interactive mode commands to read clint mtime/mtimecmp	4 years ago
Jerry Zhao	5cf439b24e	Add dump memory command to interactive mode	4 years ago
Jerry Zhao	7e8d1e6f29	Support command-line configuration of number of pmpregions	4 years ago
Scott Johnson	26c6795f2f	Merge pull request #1114 from riscv-software-src/data_optional In triggers, use optional<data> instead of {has_data, data}	4 years ago
Andrew Waterman	062ef88680	In triggers, use optional<data> instead of {has_data, data}	4 years ago
Parshintsev Anatoly	60c0c86c28	Report error if an unsupported memory configuration is detected	4 years ago
Andrew Waterman	37c8985013	Remove unused field matched_t::data	4 years ago
Andrew Waterman	e2e66015af	Merge pull request #1107 from riscv-software-src/simplify-ld-st Simplify handling of load/store/fetch slow-path cases; fix two minor trigger bugs	4 years ago
Andrew Waterman	86d9fe49ed	Set tval on illegal subforms of aes64ks1i h/t @YenHaoChen	4 years ago
Andrew Waterman	a3e8585aec	Merge pull request #1109 from riscv-software-src/dm-no-abstract-fpr Add --dm-no-abstract-fpr option.	4 years ago
Andrew Waterman	8ff186bd0f	Fix disassembly of RV64 srai.u The shift amount is 6 bits wide on RV64. As with the base ISA shifts, we ignore XLEN and unconditionally disassemble the 6-bit immediate on RV32. Partially reverts `da93bdc435`	4 years ago
Tim Newsome	1112fd33a4	Add --dm-no-abstract-fpr option. Previously FPRs could always be accessed using abstract commands. I need this to get coverage of some OpenOCD code that I broke. (See https://github.com/riscv/riscv-openocd/pull/745)	4 years ago
Andrew Waterman	7b8114f707	Don't use reexecution as the means to implement trigger-after The scheme was based on the notion that memory accesses are idempotent up until the point the trigger would've been hit, which isn't true in the case of side-effecting loads and data-value triggers. Instead, check the trigger on the next instruction fetch. To keep the perf overhead minimal, perform this check on the I$ refill path, and ensure that path is taken by flushing the I$.	4 years ago
Andrew Waterman	fd50768df9	Fix endianness bug in fetch triggers Instruction fetch is always little-endian.	4 years ago
Andrew Waterman	197f3e2640	DRY in checking triggers	4 years ago
Andrew Waterman	14410156b2	Move uncommon-case fetch functionality into fetch_slow_path	4 years ago
Andrew Waterman	6311f7513a	Move all uncommon-case store functionality into store_slow_path As a side effect, misaligned stores now behave the same as aligned stores with respect to triggers: only the first byte is checked.	4 years ago
Andrew Waterman	749ead90a5	Move all uncommon-case load functionality into load_slow_path As a side effect, misaligned loads now behave the same as aligned loads with respect to triggers: only the first byte is checked.	4 years ago
Andrew Waterman	d7edd7ac55	Remove unused variable to fix build	4 years ago
Andrew Waterman	cb7e6b840b	Merge pull request #1105 from YenHaoChen/pr-trigger-priority Fix trigger priority	4 years ago
Andrew Waterman	9b07419835	Merge pull request #1089 from riscv-software-src/fix-warnings Fix or work around ignored-qualifiers, unused-function, unused-parameter, and unused-variable warnings	4 years ago
Andrew Waterman	054a4aa579	Engage non-virtual-dtor warning in CI tests	4 years ago
Jerin Joy	f5ec721fa9	Fixed -Wnon-virtual-dtor warnings Signed-off-by: Jerin Joy <joy@rivosinc.com>	4 years ago

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2393 Commits (cefccba8cf1008691a1bb5d36bd318e281ffc635) All Branches Search

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