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riscv-isa-sim
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4060 Commits
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19 MiB
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4060 Commits (cd4f7b855327305d521818f05fc9ccc610388d23)
 

Author SHA1 Message Date
Scott Beamer 7812ee06e6 couple of more notes on debug mode
12 years ago
Scott Beamer e15f2cd699 notes on using debug mode
12 years ago
Andrew Waterman 752a7e8060 Disallow access to FCSR when FP is disabled
12 years ago
Andrew Waterman 43615c60e7 Use precompiled headers to speed up compilation
12 years ago
Andrew Waterman 8a45108918 Minor refactoring
12 years ago
Christopher Celio 3d17e24e8d Commit log now prints while interrupts are enabled.
12 years ago
Andrew Waterman 1c3a5b1d1b Only print commit log if instruction commits
12 years ago
Andrew Waterman 013657ac8c Set status.u64 to true on boot
12 years ago
Andrew Waterman acc42d79e2 fix disassembly of bnez and friends
12 years ago
Stephen Twigg e23899eae2 Merge branch 'tm'
12 years ago
Stephen Twigg 97c0aa44d3 Sync encoding in opcodes
12 years ago
Stephen Twigg 963c0825a7 Add ut_fclass_s/d hwacha (unused until encoding sync)
12 years ago
Andrew Waterman 06b8f69622 Support RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
12 years ago
Andrew Waterman a076538866 speed up compilation a bit
12 years ago
Andrew Waterman 466b679dcf New FP encoding
12 years ago
Andrew Waterman ab14719919 Add fclass.{s|d} instructions
12 years ago
Yunsup Lee e4a605049a add hwacha vfmsv instructions
12 years ago
Yunsup Lee 0a048a93eb add extensions to riscv-dis for better disassembly
12 years ago
Andrew Waterman d47f8ca5b6 Renumber uarch CSRs into custom CSR space
12 years ago
Andrew Waterman 6c99f30d78 Fix I$ simulator not making forward progress
12 years ago
Andrew Waterman b227ec194f Fix commit log when !debug
12 years ago
Andrew Waterman 49818734d3 Revert to old AUIPC definition
12 years ago
Andrew Waterman e50ddde0ff Clear EVEC LSBs, which kindly prevents a segfault
12 years ago
Andrew Waterman 1ea07ef7c5 Fix disassembly of JAL
12 years ago
Yunsup Lee 2cd631a294 commit missing definitions for uarch counters
12 years ago
Quan Nguyen 9dbe0fac5f Move half precision instructions, add vfmsv, vfmvv
12 years ago
Andrew Waterman 97b1bc610f Fix linking on Darwin
12 years ago
Christopher Celio 0346522aa6 Disasm now translates xor x0,x0,x0 as a machine-generated bubble ("-").
12 years ago
Andrew Waterman 9a9df0230f Force extension loaders to be linked in
12 years ago
Andrew Waterman 2c1ddd1781 Enable runtime loading of dynamic library with --extlib
12 years ago
Andrew Waterman ec30507bf5 Prefer libraries located in current directory
12 years ago
Andrew Waterman fb3be24671 Eliminate hwacha <-> riscv circular dependence
12 years ago
Andrew Waterman afa56de3d5 Link subproject dynamic libraries correctly
12 years ago
Andrew Waterman 017f62ac55 Merge softfloat_riscv into softfloat
12 years ago
Andrew Waterman 287a1f87ca Require libdl for dynamic linking at runtime
12 years ago
Andrew Waterman 816893bbe7 Disassemble amoxor
12 years ago
Andrew Waterman 471a5fe748 Build and use shared libraries only
12 years ago
Andrew Waterman 4a2f98e35f Build and use shared libraries
12 years ago
Andrew Waterman 127fdd1d94 Handle CSR permissions correctly
12 years ago
Andrew Waterman 2fa668a2d0 Use auto-generated trap cause numbers
12 years ago
Quan Nguyen bd9a5a429d Merge branch 'confprec'
12 years ago
Andrew Waterman 733dc842be Initialize tohost and fromhost to zero
13 years ago
Andrew Waterman 77f2815807 Improve performance for branchy code
13 years ago
Andrew Waterman 7f457c47b3 Speed things up quite a bit
13 years ago
Andrew Waterman e85cb99c5e New RDCYCLE encoding
13 years ago
Quan Nguyen 64785705a4 Remove debug printf in vsetprec
13 years ago
Quan Nguyen 05f9118e82 Add vsetprec instruction prototype
13 years ago
Andrew Waterman aedcd67ac8 Update to new privileged ISA
13 years ago
Quan Nguyen af0a019881 Merge branch 'master' of github.com:ucb-bar/riscv-isa-sim into HEAD
13 years ago
Yunsup Lee ee7867e79e fix slli/slliw encoding bug
13 years ago