3bfe3ce5ee
Add Zvabd extension.
6 months ago
5968cbe53e
Merge pull request #2242 from Steven-Li-Xiaogang/master
fix M-mode access scountovf according to Sscofpmf Version V1.0
2 months ago
c76d96d9cd
Squashed PR 2199: Fix initialization bugs and merge conflicts with per-hart start PCs
2 months ago
926d1c01d8
fix M-mode access scountovf according to Sscofpmf Version V1.0
2 months ago
591cff1610
Merge pull request #2207 from riscv-software-src/fix-2206
Only set mstatus.VS for legal vector instructions
3 months ago
a437348306
Retire dirty_vs_state macro
Reduce chance that it gets misused again in the future.
3 months ago
a665eb0337
Don't write vstart in set_vl
All callers (the vector_unit constructor and the vsetvl instructions)
already initialize or otherwise zero vstart.
3 months ago
ea29ce276c
Make sure VS is set on fault-only-first loads in all cases
We weren't setting it in the case that an exception was detected on
element 0, which is technically OK since no state changed, but is
inconsistent with how we handle regular vector loads.
3 months ago
17682e173d
Make all vector ALU instructions invoke VECTOR_END, dirtying VS
dirty_vs_state is therefore no longer needed at the top in
require_vector.
Furthermore, the vstart write in VECTOR_END dirties VS, so
dirty_vs_state is not needed.
4 months ago
e8e3a747d5
Dramatically simplify whole-register loads/stores
This makes the vstart/VS handling identical to regular vector loads/stores
3 months ago
ae1531c207
Merge pull request #2239 from riscv-software-src/fix-2238
Make minstretcfg/mcyclecfg privilege bits read-only zero as appropriate
3 months ago
114be91bbe
Remove incorrect use of static variable
It prevents modeling mixed RV32/RV64 systems.
3 months ago
0714f0f588
Simplify masking of mnstatus bits when H is toggled
3 months ago
6aa146d209
Simplify masking of medeleg bits when H is toggled
3 months ago
cdca6411ad
Simplify masking of mhpmevent bits when H is toggled
3 months ago
1d50ad3984
Make minstretcfg/mcyclecfg privilege bits read-only zero as appropriate
3 months ago
68d4514685
Merge pull request #2236 from riscv-software-src/fix-2235
Don't error out if program buffer has size 0
3 months ago
c73c3a1791
Merge pull request #2234 from hirooih/README.md-gdb-semihosting
Updated “Debugging With Gdb” to use semihosting
3 months ago
ab21eb0e4c
Merge pull request #2165 from FrancescoScappatura-Ax/dtb_discovery_feature
DTB discovery feature
3 months ago
5564ca81b7
Don't error out if program buffer has size 0
Resolves #2235
3 months ago
82742081e9
Updated “Debugging With Gdb” to use semihosting
- make the sample program as a typical C program
that uses the stack and semihosting (#155 ).
- use the default crt0.o and linker script.
Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>
2 years ago
2c94ea431e
DTB discovery feature
3 months ago
b8eacc25b8
Merge pull request #2232 from riscv-software-src/fix-2230
Disallow delegation of misaligned-fetch exceptions when IALIGN=16
3 months ago
4adab496a2
Disallow delegation of misaligned-fetch exceptions when IALIGN=16
Fixes #2230
3 months ago
875a7ee66a
Merge pull request #2228 from abejgonzalez/patch-2
Modify in_bits to check in_valid before accessing
3 months ago
78762796e8
Modify in_bits to check in_valid before accessing
Signed-off-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
3 months ago
eb6586e3de
Merge pull request #2227 from riscv-software-src/fix-2221
Raise correct trap in U-mode on indirect CSRs when !mstateen.csrind
3 months ago
aea74cb694
Raise correct trap in U-mode on indirect CSRs when !mstateen.csrind
Fixes #2221
3 months ago
98ccf030bb
Merge pull request #2221 from DymShanks/fix/vu-mode-sireg
Fix: Enforce virtual_instruction trap for VU-mode indirect CSR access
4 months ago
49d1d2a802
Fix: Enforce virtual_instruction trap for VU-mode indirect CSR access
4 months ago
7655ac0843
Merge pull request #2223 from riscv-software-src/fix-deps
Regularize extension-dependency handling
4 months ago
8b802199fb
Have Zabha imply extensions rather than erroring if not present
4 months ago
5c142baf88
Have ZC* imply extensions rather than erroring if not present
4 months ago
27ecd02d6b
Have Zvfofp4min imply extensions rather than erroring if not present
4 months ago
1a2af0362e
Clean up handling of Zcf
4 months ago
ac939da203
Have V imply extensions rather than erroring if not present
4 months ago
466d1b0e4c
Have Z[v]fbfmin imply extensions rather than erroring if not present
4 months ago
8b22afdbd9
Have Zvfhmin imply extensions rather than erroring if not present
4 months ago
a91c0a9f51
Factor out add_extension method
4 months ago
e9571d4498
Have Zfhmin imply extensions rather than erroring if not present
4 months ago
715906f416
Have Zclsd imply extensions rather than erroring if not present
4 months ago
978f96a992
Have Zicfiss imply extensions rather than erroring if not present
4 months ago
9882cd202b
Zicfiss depends on Zaamo
So, no need to check for Zaamo in the instruction definitions
4 months ago
e7901f43aa
Don't log commits in snippy tests
Doing so adds too much output to the CI logs.
4 months ago
9cea90bd28
Merge pull request #2224 from riscv-software-src/add-vector-test
Add simple vector extension test to CI
4 months ago
52e6a75584
Echo CI commands to ease debugging
4 months ago
6ff9d9ccd5
Add simple vector extension test to CI
4 months ago
6dda4896cb
Merge pull request #2198 from riscv-software-src/fix-amocas-q
Fix triggers for accesses wider than XLEN
4 months ago
dfbd749842
Make reg_from_bytes a bit less gross
I'd like to remove this routine eventually, but let's make it a bit less
visually unappealing in the meantime.
5 months ago
497e3d830d
DRY in logging code
5 months ago
Zhibo Hong
Andrew Waterman
nabudahab
steven
Hiroo HAYASHI
Francesco Scappatura
Abraham Gonzalez
DymShanks