riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
YenHaoChen	a80115ddf4	typo: correct sstateen CSR address	2 years ago
Andrew Waterman	b98de6f689	Merge pull request #1539 from riscv-software-src/fix-signed-overflow Fix UB on signed overflow in mulh routine	2 years ago
Andrew Waterman	1cc3a1fab1	Fix UB on signed overflow in mulh routine We want to evaluate whether the product of a and b is zero mod 2^64, but the product might overflow, resulting in UB. If we instead perform the computation in unsigned arithmetic, the overflow behavior is defined. Resolves #1538	2 years ago
phantom1003	a93f8b8c5a	build: bump configure to autoconf 2.71	2 years ago
phantom1003	dddf60e994	build: fix broken configure The configure generated by Ubuntu22's upstream autoconf (2.71) is broken. DEFAULT_VARCH was expanded incorrectly, causing the generated line to be truncated from the comma. Since this macro is a constant and doesn't depend on environment variables, it doesn't require shell expansion.	2 years ago
Tan En De	221eb465c6	riscv: sim.cc: Consider cpu-map node in cpus node cpu-map node may be present in cpus node. `124e46a865` So this commit adds logic to consider that by skipping cpu-map node. Signed-off-by: Tan En De <ende.tan@starfivetech.com>	3 years ago
Jerry Zhao	a729aff03d	Merge pull request #1535 from riscv-software-src/no_install_libfdt Don't install spike's libfdt to avoid conflicts with system libfdt	2 years ago
Jerry Zhao	437ae42895	Don't install spike's libfdt to avoid conflicts with system libfdt	2 years ago
Jerry Zhao	4d8651be94	Merge pull request #1313 from endeneer/fdt-parse-clint-sifive riscv: sim.cc: Parse for "sifive,clint0" if "riscv,clint0" is absent	2 years ago
Jerry Zhao	f9cd7ee5cf	Merge pull request #1314 from endeneer/fdt-parse-plic-sifive riscv: sim.cc: Parse for other compatible strings if "riscv,plic0" is absent	2 years ago
Andrew Waterman	72d23d647c	Merge pull request #1448 from ved-rivos/adue_fix A/D updates in G-stage PTE	2 years ago
Tan En De	87690a90c7	riscv: sim.cc: Parse for "sifive,plic-1.0.0" if "riscv,plic0" is absent "riscv,plic0" and "sifive,plic-1.0.0" in device tree's "compatible" string point to the same driver, as can be seen from drivers/irqchip/irq-sifive-plic.c in Linux kernel. `5873ba5591` The other two "compatible" strings below isn't included, because of their different plic behavior (plic_edge_init instead of plic_init as explained in the Linux commit). - "andestech,nceplic100" - "thead,c900-plic" Signed-off-by: Tan En De <ende.tan@starfivetech.com>	3 years ago
Tan En De	f1c000837c	riscv: sim.cc: Parse for "sifive,clint0" if "riscv,clint0" is absent "riscv,clint0" and "sifive,clint0" in device tree's "compatible" string point to the same driver, as can be seen from drivers/clocksource/timer-clint.c in Linux kernel. `2ac6795fcc` Signed-off-by: Tan En De <ende.tan@starfivetech.com>	3 years ago
Jerry Zhao	19078c1782	Merge pull request #1506 from riscv-software-src/fix-1505 Don't enforce alignment constraints vwsll.v[xi] rs1 arg	2 years ago
Jerry Zhao	f1e0be8404	Merge pull request #1526 from riscv-software-src/default_cfg Add default cfg_t and debug_module_config_t constructor to libriscv	2 years ago
Andrew Waterman	218c4a3ce8	Merge pull request #1532 from Madman-Hugo/fix-fmvh_x_d fix fmvh_x_d.h rv32 sign-extended	2 years ago
Madman	2e2a8cb5c1	fix fmvh_x_d.h rv32 sign-extended Signed-off-by: Madman <1017747824@qq.com>	2 years ago
Jerry Zhao	0232396e7e	Rely on default initializer to provide debug_module_config_t defaults	2 years ago
Jerry Zhao	4b30f35aae	Use brace initializers for debug_module_config_t defaults	2 years ago
Jerry Zhao	ab10e576e1	Remove old explicit-fields cfg_t constructor, switch to default constructor	2 years ago
Jerry Zhao	0ee120bfae	Add cfg_t default constructor with default settings	2 years ago
Jerry Zhao	ae889cb849	Remove cfg_arg_t from cfg_t Argument parsing should be scoped to the code which constucts cfg_t	2 years ago
Andrew Waterman	e04f5f321c	Merge pull request #1531 from riscv-software-src/zimop-v3 Add unratified Zimop extension	2 years ago
Andrew Waterman	84f1dbaf8e	Add Zimop extension	2 years ago
Andrew Waterman	6b2ea346b5	Fix formatting	2 years ago
Andrew Waterman	f3b8345c21	Update encoding.h	2 years ago
Andrew Waterman	f6b868c645	Merge pull request #1530 from riscv-software-src/ci-commit-order Per-commit CI should start from oldest commit	2 years ago
Jerry Zhao	ca631b621b	Per-commit CI should start from oldest commit	2 years ago
Jerry Zhao	1f466dfd15	Merge pull request #1522 from ucb-bar/device-plugin-api Fix Spike --device option to pass on args to downstream plugins	2 years ago
joey0320	b98e922cb4	Fix Spike --device option to pass on args to downstream plugins	2 years ago
Andrew Waterman	d94fe56b4f	Merge pull request #1523 from YenHaoChen/patch-1 miselect: support miselect when enabling smcsrind	2 years ago
YenHaoChen	bdfbd54959	refactor: single statement of declaration and initialization on miselect, siselect, and vsiselect	2 years ago
YenHaoChen	aa0bbeb296	miselect: support miselect when enabling smcsrind Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>	2 years ago
Andrew Waterman	e46586e2b5	Merge pull request #1513 from riscv-software-src/sbbusyerror Add configurable system bus access delay	2 years ago
Tim Newsome	0d85419fec	Test OpenOCD that can deal with sbbusyerror.	2 years ago
Tim Newsome	650c15caf9	Add SBA write delay. This is helpful to test OpenOCD behavior when sbbusyerror is set.	2 years ago
Tim Newsome	bf6ce5e1cb	Add SBA read delay. This is helpful to test OpenOCD behavior when sbbusyerror is set.	2 years ago
Andrew Waterman	d74ab37106	Merge pull request #1517 from YenHaoChen/patch-1 typo: vwsll.vi: fix a typo on disassembling vwsll.vi	2 years ago
YenHaoChen	e9ae2287e1	typo: vwsll.vi: fix a typo on disassembling vwsll.vi Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>	2 years ago
Andrew Waterman	0c1397661c	Merge pull request #1516 from YenHaoChen/pr-dcsr-ebreakx fix: dcsr.ebreak(v)[su] hardwired to 0 if unsupport corresponding privilege modes	2 years ago
YenHaoChen	a62b69a889	fix: dcsr.ebreak(v)[su] hardwired to 0 if unsupport corresponding privilege modes	2 years ago
Andrew Waterman	3bc4f0f8fd	Merge pull request #1514 from f0rget-the-sad/multi-rb remote_bitbang: make send_buf class member	2 years ago
Volodymyr Fialko	a68f2caafb	remote_bitbang: make send_buf class member Currently send buffer is static variable in function, which makes it's impossible to have multiple concurrent instances of remote bitbang class, since all of them would share this static buffer. Thus, make send_buf a class member. Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>	2 years ago
Andrew Waterman	90aa49f85b	Merge pull request #1511 from YenHaoChen/pr-stimecmp stimecmp: perform menvcfg.STCE permission check when accessing vstimecmp in HS-mode	2 years ago
YenHaoChen	6e6885feed	stimecmp: perform menvcfg.STCE permission check when accessing vstimecmp in HS-mode The spec requires menvcfg.STCE=1 on accessing stimecmp or vstimecmp in a mode other than M-mode. The previous implementation does not check the permission on accessing vstimecmp in HS-mode. This commit fixes the issue by moveing the permission check from virtualized_stimecmp_csr_t to stimecmp_csr_t, which implements the vstimecmp.	2 years ago
Andrew Waterman	4841ad0238	Fix FMVP.D.X implementation Resolves #1507	2 years ago
Andrew Waterman	874ac597c5	Don't enforce alignment constraints vwsll.v[xi] rs1 arg rs1 doesn't represent a vector arg in this case, so the instructions were broken for (rs1 % ceil(LMUL)) != 0. Resolves #1505	2 years ago
Tim Newsome	be5dee0baf	Merge pull request #1500 from riscv-software-src/debug_tests Update debug smoketest action.	2 years ago
Tim Newsome	ca84e5325e	Update debug smoketest action. To get https://github.com/riscv-software-src/riscv-tests/pull/522, which fixes an intermittent failure.	2 years ago
Andrew Waterman	4f916978cd	Merge pull request #1498 from f0rget-the-sad/htif-stop-on-signal fesvr/htif: allow exit on SIGINT.	2 years ago

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