riscv-isa-sim

Commit Graph

Author	SHA1	Message	Date
Mark Lai	c6e2b703c5	Include cerrno in fesvr/elfloader.cc It caused compile error "use of undeclared identifier 'errno'" at line 26 and 33. I Add #include <cerrno> in fesvr/elfloader.cc to fix error and compile successfully.	3 years ago
Andrew Waterman	5a499ef718	Merge pull request #1436 from ved-rivos/hade_to_adue Rename envcfg.HADE to envcfg.ADUE	3 years ago
Ved Shanbhogue	07c2e2bfcb	rename envcfg.HADE to envcfg.ADUE	3 years ago
Andrew Waterman	ec3c9357ec	Merge pull request #1427 from YenHaoChen/pr-textra-sbytemask triggers: fix textra.sbytemask	3 years ago
Andrew Waterman	c59e80e980	Merge pull request #1381 from rivosinc/smcntrpmf_feature Add Smcntrpmf support	3 years ago
Atul Khare	c927773dd1	Add Smcntrpmf functionality If Smcntrpmf is enabled, mcycle / minstret increment only if counting for the privilege level isn't inhibited in mcyclecfg / minstretcfg.	3 years ago
Atul Khare	62178539f8	Add prv_changed / v_changed fields to state This tracks whether the privilege / virtual mode was changed by the execution of the current instruction.	3 years ago
Atul Khare	1c91fd56ba	Regenerate encoding.h	3 years ago
YenHaoChen	63379810b4	triggers: fix textra.sbytemask Ignore corresponding bytes to the scontext and textra.svalue. Cast 0xff to reg_t for the 34-bit textra64.svalue.	3 years ago
Andrew Waterman	60c08b1ea5	Merge pull request #1383 from rivosinc/sscrind_feature Add Smcsrind / Sscsrind support	3 years ago
Scott Johnson	4d0171931c	Merge pull request #1416 from YenHaoChen/pr-xenvcfg-cbie Legalize xenvcfg.CBIE	3 years ago
YenHaoChen	e7e1880111	legalize henvcfg.CBIE The value 2 of henvcfg.CBIE is reserved. This commit legalizes it to 0. Reference: https://github.com/riscv/riscv-CMOs/issues/65	3 years ago
YenHaoChen	7f22022e1a	legalize senvcfg.CBIE The value 2 of senvcfg.CBIE is reserved. This commit legalizes it to 0. Reference: https://github.com/riscv/riscv-CMOs/issues/65	3 years ago
YenHaoChen	f6e7338b26	legalize menvcfg.CBIE The value 2 of menvcfg.CBIE is reserved. This commit legalizes it to 0 by adding a specialized class envcfg_csr_t. Reference: https://github.com/riscv/riscv-CMOs/issues/65	3 years ago
Andrew Waterman	5e375b98d9	Merge pull request #1422 from mbgg/fix-prefix-warning Fix compilation warning in riscv/execute.cc	3 years ago
Jerry Zhao	1b41ed3c48	Merge pull request #1415 from michalt/memt-virtual Make methods of `mem_t` virtual to allow overriding	3 years ago
Matthias Brugger	6bfab0e212	Fix compilation warning in riscv/execute.cc ../riscv/execute.cc: In function ‘void commit_log_print_insn(processor_t*, reg_t, insn_t)’: ../riscv/execute.cc:132:16: warning: ‘prefix’ may be used uninitialized [-Wmaybe-uninitialized] 132 \| fprintf(log_file, " %c%-2d ", prefix, rd); \| ~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../riscv/execute.cc:88:10: note: ‘prefix’ was declared here 88 \| char prefix; \| ^~~~~~	3 years ago
Michal Terepeta	cb01351666	Introduce `abstract_mem_t` to allow custom implementations This change allows to create custom implementations of `abstract_mem_t` and inject them when constructing `sim_t`. The current `mem_t` implementation remains unchanged. Fixes #1408.	3 years ago
Atul Khare	bc5842f945	Add Smcsrind/Sscsrind support This adds the following CSRs: miselect (0x350), mireg (0x351), mireg2/3 (0x352, 0x353), mireg4-6 (0x355 - 0x357), siselect (0x150), sireg (0x151), sireg2/3 (0x152, 0x153), sireg4-6 (0x155 - 0x157), vsiselect (0x250), vsireg (0x251), mireg2/3 (0x252, 0x253), vsireg4-6 (0x255 - 0x257). Presently, attempts to read / write from ireg? registers will fail, and future extensions will provide proxy CSR mappings for the respective ?ireg CSRs.	3 years ago
Atul Khare	a6bc48b95e	Rengenerate encoding.h	3 years ago
Atul Khare	2d80209347	Add Smcsrind/Sscsrind extensions	3 years ago
Andrew Waterman	432c9ee976	Merge pull request #1413 from YenHaoChen/pr-mcontrol-cbo-zero-tval mcontrol/mcontrol6 on CBO	3 years ago
YenHaoChen	8658429647	mcontrol/mcontrol6 triggers on cbo.flush/clean The mcontrol/mcontrol6 store address before has a higher priority over page faults and access faults. Thus, trigger checking should before the translate(). This commit checks all address of the cache block. Reference: Debug spec 1.0, 5.5.3 Cache Operations Reference: CMO spec 1.0.1, 2.5.4 Breakpoint Exceptions and Debug Mode Entry	3 years ago
Andrew Waterman	371353288e	Merge pull request #1419 from poemonsense/fix-fetch-order mmu: fetch instruction bytes in ascending order	3 years ago
Yinan Xu	93aad1d355	mmu: fetch instruction bytes in ascending order Fetching instruction bytes in descending order would result in wrong xtval update values.	3 years ago
YenHaoChen	4aea5a05ad	fix mcontrol's tval on cbo_zero The tval should capture the effective address on an (trigger) exception. Reference: https://github.com/riscv/riscv-CMOs/issues/55	3 years ago
YenHaoChen	faceda27e6	refactor: mcontrol/mcontrol6: extend check_triggers() with tval parameter	3 years ago
Jerry Zhao	e85d2923a5	Merge pull request #1409 from riscv-software-src/ext-symbols Add all symbols from extension.o to spike main	3 years ago
Jerry Zhao	3b0d3c2004	build: Force inclusion of all symbols from extension.o in spike-main The --extension feature requires that all symbols in extension.o be available when the libraries are dynamically loaded by dlopen. Prepending extension.o to the linker command adds the otherwise omitted symbols to spike's dynamic symbol table.	3 years ago
Jerry Zhao	fe05760445	build: Support project-defined LDFLAGS	3 years ago
Jerry Zhao	2eb2b40102	Remove dependency of isa_parser_t on extension_t	3 years ago
Jerry Zhao	47ab8926b0	Move isa_parser_t to libdisasm out of libriscv	3 years ago
Andrew Waterman	ed5dccb291	Merge pull request #1402 from riscv-software-src/zicond-default-disasm Disassemble Zicond by default	3 years ago
Andrew Waterman	37bef605d5	Disassemble Zicond by default In general, the strategy has been that the disassembler enables a maximal set of non-conflicting extensions, thereby doing the right thing for the largest number of users.	3 years ago
Andrew Waterman	e9848ed305	Merge pull request #1394 from riscv-software-src/unavailable Let debugger control hart availability	3 years ago
Tim Newsome	ea6740350f	Let debugger control hart availability This change lets me test OpenOCD's behavior when harts become available. It only affects how things look to the debugger. Harts that are "unavailable" still execute code as usual. Control is implemented through the 2 LSBs of the DMCUSTOM register in the Debug Module.	3 years ago
Jerry Zhao	09a3c644d4	Merge pull request #1389 from riscv-software-src/devices sim_t: Add sim_t::add_device()	3 years ago
Jerry Zhao	2d61da3622	sim_t: Add sim_t::add_device() API This is public so libspike users can precisely configure the device bus without going through the DTS interface	3 years ago
Andrew Waterman	f45f7269b7	Merge pull request #1337 from YenHaoChen/pr-icount-bugfix triggers: icount: not to decrease on firing icount trigger with Debug Mode action	3 years ago
YenHaoChen	fb18fe2d93	triggers: icount: not to decrease on firing icount trigger with Debug Mode action The icount decreases on firing beakpoint action but not on entering Debug Mode action. Reference: https://github.com/riscv/riscv-debug-spec/issues/842	3 years ago
Andrew Waterman	71f5a8fd1b	Merge pull request #1338 from aap-sc/aap-sc/sb_read_write_fixup fixup sb_write/sb_read to handle exceptions	3 years ago
Andrew Waterman	85d7f869e9	Merge pull request #1391 from demin-han/master Remove duplicate compile options	3 years ago
demin.han	7ac808ee1b	Remove duplicate compile options	3 years ago
Jerry Zhao	d8b6fc534f	Merge pull request #1374 from riscv-software-src/devices Use device factories to control dts-construction/dts-parsing/device-instantiation	3 years ago
Jerry Zhao	b87c6e64d0	debug: Remove debug_module_t::add_device, its redundant	3 years ago
Jerry Zhao	186c619fb3	devices: Switch plugin device interface to use device_factory_t Plugins should now implement and register a device_factory_t to configure how that device should be parsed from a FDT, and an optional default DTS string. This drops support for command-line flag-based device configuration	3 years ago
Jerry Zhao	701029d28b	ns16550_t: ns16550 should parse interrupt id from the fdt	3 years ago
Jerry Zhao	37e50ad499	dts: Expose fdt_get_node_addr_size function in header	3 years ago
Jerry Zhao	bb2754c201	dts_t: Add dts.h to list of installed headers	3 years ago
Jerry Zhao	16be75973a	libfdt: Install libfdt and libfdt.h	3 years ago

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